71V016SA12BFG IDT, 71V016SA12BFG Datasheet - Page 6

• Manufacturer Part Number: 71V016SA12BFG
• Description: SRAM
• Manufacturer: IDT

Specifications of 71V016SA12BFG

• Product Category: SRAM
• Rohs: yes
• Part # Aliases: IDT71V016SA12BFG

Timing Waveform of Read Cycle No. 2
NOTES:
1. WE is HIGH for Read Cycle.
2. Address must be valid prior to or coincident with the later of CS, BHE, or BLE transition LOW; otherwise t
3. Transition is measured ±200mV from steady state.
Timing Waveform of Write Cycle No. 1 (WE Controlled Timing)
NOTES:
1. A write occurs during the overlap of a LOW CS, LOW BHE or BLE, and a LOW WE.
2. OE is continuously HIGH. If during a WE controlled write cycle OE is LOW, t
3. During this period, I/O pins are in the output state, and input signals must not be applied.
4. If the CS LOW or BHE and BLE LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.
5. Transition is measured ±200mV from steady state.
IDT71V016SA, 3.3V CMOS Static RAM
1 Meg (64K x 16-Bit)
ADDRESS
ADDRESS
on the bus for the required t
BHE, BLE
DATA
BHE
DATA
DATA
,
OUT
BLE
CS
OE
WE
OUT
CS
IN
DW
PREVIOUS DATA VALID
. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse is as short as the specified t
t
AS
t
CLZ
(3)
(3)
t
t
ACS
WHZ
t
t
BLZ
AA
t
AW
(5)
t
t
(2)
BE
CW
WP
(3)
t
OLZ
must be greater than or equal to t
(2)
(2)
t
t
BW
WC
t
RC
6.42
(3)
6
t
OE
t
WP
(1)
DATA
t
DW
AA
is the limiting parameter.
IN
Commercial and Industrial Temperature Ranges
VALID
WHZ
+ t
DATA
DW
t
t
DH
t
to allow the I/O drivers to turn off and data to be placed
OW
WR
OUT
(5)
VALID
t
OH
t
t
CHZ
BHZ
t
OHZ
(3)
(3)
(3)
DATA VALID
t
t
CHZ
BHZ
(1,2,4)
(5)
(5)
3834 drw 07
3834 drw 08
WP
.