7028L20PF IDT, 7028L20PF Datasheet - Page 2

• Manufacturer Part Number: 7028L20PF
• Description: SRAM
• Manufacturer: IDT

Specifications of 7028L20PF

• Part # Aliases: IDT7028L20PF

Pin Configurations
Description
IDT7028 is designed to be used as a stand-alone 1024K-bit Dual-Port
RAM or as a combination MASTER/SLAVE Dual-Port RAM for 32-bit-or-
more word systems. Using the IDT MASTER/SLAVE Dual-Port RAM
approach in 32-bit or wider memory system applications results in full-
speed, error-free operation without the need for additional discrete logic.
NOTES:
1. All Vcc pins must be connected to power supply.
2. All GND pins must be connected to ground.
3. Package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part marking.
IDT7028L
High-Speed 64K x 16 Dual-Port Static RAM
The IDT7028 is a high-speed 64K x 16 Dual-Port Static RAM. The
This device provides two independent ports with separate control,
11/19/01
INDEX
I/O
I/O
I/O
I/O
I/O
I/O
SEM
R/W
CE
CE
GND
GND
A
A
A
A
A
A
OE
UB
LB
Vcc
A
NC
NC
10L
11L
12L
13L
14L
15L
14L
13L
12L
11L
10L
15L
9L
0L
1L
L
L
L
L
L
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
(1,2,3)
100-Pin TQFP
Top View
IDT7028PF
PN100-1
2
address, and I/O pins that permit independent, asynchronous access for
reads or writes to any location in memory. An automatic power down
feature controlled by the chip enables (CE
circuitry of each port to enter a very low standby power mode.
devices typically operate on only 1W of power.
(4)
Fabricated using IDT’s CMOS high-performance technology, these
The IDT7028 is packaged in a 100-pin Thin Quad Flatpack (TQFP).
(5)
Industrial and Commercial Temperature Ranges
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
0
and CE
4836 drw 02
A
NC
A
A
A
A
A
A
NC
LB
UB
CE
CE
SEM
GND
R/W
OE
GND
GND
I/O
I/O
I/O
I/O
I/O
I/O
1
10R
11R
12R
13R
14R
15R
9R
) permit the on-chip
R
R
0R
R
15R
14R
13R
12R
11R
10R
1R
R
R