71016S20PHG IDT, 71016S20PHG Datasheet
71016S20PHG
Specifications of 71016S20PHG
Related parts for 71016S20PHG
71016S20PHG Summary of contents
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... CMOS technology. This state-of-the-art technology, combined with innovative circuit design techniques, provides a cost-effective solution for high-speed memory needs. The IDT71016 has an output enable pin which operates as fast as 7ns, with address access times as fast as 12ns. All bidirectional inputs and outputs of the IDT71016 are TTL-compatible and operation is from a single 5V supply ...
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... IDT71016, CMOS Static RAM 1 Meg (64K x 16-bit) Pin Configurations SO44 SO44 A15 18 A14 19 A13 20 A12 SOJ/TSOP Top View Truth Table ( ...
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... GND 3210 tbl NOTE (min.) = –1.5V for pulse width less than tRC/2, once per cycle. IL Capacitance (T = +25° 1.0MHz, SOJ/TSOP Package) A Symbol I/O NOTE: 1. This parameter is guaranteed by device characterization, but not production tested. Test Conditions V = Max ...
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... IDT71016, CMOS Static RAM 1 Meg (64K x 16-bit) AC Test Conditions Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels AC Test Load AC Test Loads DATA OUT 30pF* Figure 1. AC Test Load ∆t t AA, (Typical, ns) GND to 3.0V 1.5ns 1.5V 1.5V See Figure 1, 2 and 3 ...
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... IDT71016, CMOS Static RAM 1 Meg (64K x 16-bit) AC Electrical Characteristics Symbol READ CYCLE t Read Cycle Time RC t Address Access Time AA t Chip Select Access Time ACS (1) Chip Select Low to Output in Low-Z t CLZ (1) Chip Select High to Output in High-Z t CHZ t Output Enable Low to Output Valid ...
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... IDT71016, CMOS Static RAM 1 Meg (64K x 16-bit) Timing Waveform of Read Cycle No. 2 ADDRESS OE CS BHE, BLE DATA OUT NOTES HIGH for Read Cycle. 2. Address must be valid prior to or coincident with the later of CS, BHE, or BLE transition LOW; otherwise t 3. Transition is measured ±200mV from steady state. ...
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... IDT71016, CMOS Static RAM 1 Meg (64K x 16-bit) Timing Waveform of Write Cycle No. 2 (CS Controlled Timing) ADDRESS BHE BLE , WE DATA OUT DATA IN Timing Waveform of Write Cycle No. 3 (BHE, BLE Controlled Timing) ADDRESS BHE BLE , WE DATA OUT DATA IN NOTES write occurs during the overlap of a LOW CS, LOW BHE or BLE, and a LOW WE. ...
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... IDT71016, CMOS Static RAM 1 Meg (64K x 16-bit) Ordering Information 71016 Device Power Speed Type XXX X X Package Process/ Temperature Range 6.42 8 Commercial and Industrial Temperature Ranges Blank Commercial (0°C to +70°C) I Industrial (-40°C to +85°C) Restricted hazardous G substance device. Y 400-mil SOJ (SO44-1) ...
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... Pg. 8 CORPORATE HEADQUARTERS 6024 Silver Creek Valley Roa San Jose, CA 951 The IDT logo is a registered trademark of Integrated Device Technology, Inc. Updated to new format Expressed commercial and industrial ranges on DC Electrical table Expressed commercial and industrial ranges on AC Electrical table Revised footnotes on Write Cycle No. 1 diagram Revised footnotes on Write Cycle No ...