MAX16046ETN+CK4 Maxim Integrated, MAX16046ETN+CK4 Datasheet - Page 51

• Manufacturer Part Number: MAX16046ETN+CK4
• Description: Supervisory Circuits 12Ch EEPROM Prob System Manager
• Manufacturer: Maxim Integrated
• Series: MAX16046, MAX16048r

Specifications of MAX16046ETN+CK4

• Rohs: yes

The send byte protocol allows the master device to
send one byte of data to the slave device (see Figure
12). The send byte presets a register pointer address
for a subsequent read or write. The slave sends a
NACK instead of an ACK if the master tries to send a
memory address or command code that is not allowed.
If the master sends 94h or 95h, the data is ACK,
because this could be the start of the write block or
read block. If the master sends a STOP condition
before the slave asserts an ACK, the internal address
pointer does not change. If the master sends 96h, this
signifies a software reboot. The send byte procedure is
the following:
1) The master sends a START condition.
2) The master sends the 7-bit slave address and a
3) The addressed slave asserts an ACK on SDA.
4) The master sends an 8-bit memory address or com-
5) The addressed slave asserts an ACK (or NACK) on
6) The master sends a STOP condition.
The receive byte protocol allows the master device to
read the register content of the MAX16046/MAX16048
(see Figure 12). The EEPROM or register address must
be preset with a send byte or write word protocol first.
Once the read is complete, the internal pointer increas-
es by one. Repeating the receive byte protocol reads
the contents of the next address. The receive byte pro-
cedure follows:
1) The master sends a START condition.
2) The master sends the 7-bit slave address and a
3) The addressed slave asserts an ACK on SDA.
4) The slave sends 8 data bits.
5) The master asserts a NACK on SDA.
6) The master generates a STOP condition.
The write byte protocol (see Figure 12) allows the mas-
ter device to write a single byte in the default page,
extended page, or EEPROM page, depending on
System Managers with Nonvolatile Fault Registers
write bit (low).
mand code.
SDA.
read bit (high).
12-Channel/8-Channel EEPROM-Programmable
Receive Byte
Write Byte
Send Byte
which page is currently selected. The write byte proce-
dure is the following:
1) The master sends a START condition.
2) The master sends the 7-bit slave address and a
3) The addressed slave asserts an ACK on SDA.
4) The master sends an 8-bit memory address.
5) The addressed slave asserts an ACK on SDA.
6) The master sends an 8-bit data byte.
7) The addressed slave asserts an ACK on SDA.
8) The master sends a STOP condition.
To write a single byte, only the 8-bit memory address
and a single 8-bit data byte are sent. The data byte is
written to the addressed location if the memory address
is valid. The slave will assert a NACK at step 5 if the
memory address is not valid.
The read byte protocol (see Figure 12) allows the mas-
ter device to read a single byte located in the default
page, extended page, or EEPROM page depending on
which page is currently selected. The read byte proce-
dure is the following:
1) The master sends a START condition.
2) The master sends the 7-bit slave address and a
3) The addressed slave asserts an ACK on SDA.
4) The master sends an 8-bit memory address.
5) The addressed slave asserts an ACK on SDA.
6) The master sends a REPEATED START condition.
7) The master sends the 7-bit slave address and a
8) The addressed slave asserts an ACK on SDA.
9) The slave sends an 8-bit data byte.
10) The master asserts a NACK on SDA.
11) The master sends a STOP condition.
If the memory address is not valid, it is NACKed by the
slave at step 5 and the address pointer is not modified.
write bit (low).
write bit (low).
read bit (high).
Read Byte
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