MCIMX6Q4AVT10ACR Freescale Semiconductor, MCIMX6Q4AVT10ACR Datasheet - Page 64
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MCIMX6Q4AVT10ACR
Manufacturer Part Number
MCIMX6Q4AVT10ACR
Description
Processors - Application Specialized i.MX6Q
Manufacturer
Freescale Semiconductor
Type
Multimedia Applicationsr
Datasheet
1.MCIMX6Q6AVT10AC.pdf
(166 pages)
Specifications of MCIMX6Q4AVT10ACR
Core
ARM Cortex A9
Processor Series
i.MX6
Data Bus Width
32 bit
Maximum Clock Frequency
1 GHz
Data Ram Size
256 KB
Operating Supply Voltage
1.05 V to 1.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Package / Case
FCBGA-624
Interface Type
I2C, I2S, UART, USB
Memory Type
L1/L2 Cache, ROM, SRAM
Minimum Operating Temperature
- 40 C
Number Of Timers
2
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Electrical Characteristics
Figure 28
Table
1
2
3
64
To receive the reported setup and hold values, write calibration should be performed in order to locate the DRAM_SDQSx_P
in the middle of DRAM_DATAxx window.
All measurements are in reference to Vref level.
Measurements were done using balanced load and 25 resistor from outputs to DRAM_VREF.
LP17
LP18
LP21
LP22
LP23
ID
47.
DRAM_SDCLKx_P
DRAM_SDCLKx_N
DRAM_SDQSx_P (output)
DRAM_DATAxx (output)
DRAM_DQMx (output)
shows the LPDDR2 write timing diagram. The timing parameters for this diagram appear in
DRAM_DATAxx and DRAM_DQMx setup time to DRAM_SDQSx_P
(differential strobe)
DRAM_DATAxx and DRAM_DQMx hold time to DRAM_SDQSx_P
(differential strobe)
DRAM_SDQSx_P latching rising transitions to associated clock edges
DRAM_SDQSx_P high level width
DRAM_SDQSx_P low level width
i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2
LP21
LP17
LP17
Parameter
Figure 28. LPDDR2 Write Cycle
Table 47. LPDDR2 Write Cycle
Data
DM
LP18
LP18
Data
DM
LP17
LP17
Data
DM
LP22
Data
DM
LP23
LP18
LP18
Data
DM
Symbol
t
t
t
DQSH
DQSS
DQSL
t
t
DS
DH
Data
DM
CK = 532 MHz
-0.25
Freescale Semiconductor
Min
235
235
0.4
0.4
Data
DM
+0.25
Max
—
—
—
—
Data
DM
Unit
tCK
tCK
tCK
ps
ps
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