MCIMX6Q4AVT10ACR Freescale Semiconductor, MCIMX6Q4AVT10ACR Datasheet - Page 62
MCIMX6Q4AVT10ACR
Manufacturer Part Number
MCIMX6Q4AVT10ACR
Description
Processors - Application Specialized i.MX6Q
Manufacturer
Freescale Semiconductor
Type
Multimedia Applicationsr
Datasheet
1.MCIMX6Q6AVT10AC.pdf
(166 pages)
Specifications of MCIMX6Q4AVT10ACR
Core
ARM Cortex A9
Processor Series
i.MX6
Data Bus Width
32 bit
Maximum Clock Frequency
1 GHz
Data Ram Size
256 KB
Operating Supply Voltage
1.05 V to 1.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Package / Case
FCBGA-624
Interface Type
I2C, I2S, UART, USB
Memory Type
L1/L2 Cache, ROM, SRAM
Minimum Operating Temperature
- 40 C
Number Of Timers
2
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Electrical Characteristics
1
2
3
Figure 26
in
1
2
3
62
DDR22 DRAM_SDQSx_P high level width
DDR23 DRAM_SDQSx_P low level width
To receive the reported setup and hold values, write calibration should be performed in order to locate the DRAM_SDQSx_P
in the middle of DRAM_DATAxx window.
All measurements are in reference to Vref level.
Measurements were taken using balanced load and 25 resistor from outputs to DRAM_VREF.
To receive the reported setup and hold values, read calibration should be performed in order to locate the DRAM_SDQSx_P
in the middle of DRAM_DATAxx window.
All measurements are in reference to Vref level.
Measurements were done using balanced load and 25 resistor from outputs to DRAM_VREF.
Table
ID
DRAM_SDCLKx_P
DRAM_SDCLKx_N
DRAM_SDQSx_P(input)
DRAM_DATAxx (input)
DDR26
45.
ID
shows the DDR3/DDR3L read timing diagram. The timing parameters for this diagram appear
Minimum required DRAM_DATAxx valid window width
i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2
Table 44. DDR3/DDR3L Write Cycle (continued)
Figure 26. DDR3/DDR3L Read Cycle
Parameter
Table 45. DDR3/DDR3L Read Cycle
Parameter
DATA
DDR26
DATA
DATA
DATA
Symbol
—
DATA
Min
450
CK = 532 MHz
Symbol
t
t
DQSH
DQSL
DATA
Freescale Semiconductor
CK = 532 MHz
0.45
0.45
Min
Max
—
DATA
Max
0.55
0.55
Unit
ps
DATA
Unit
tCK
tCK
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