MCIMX251AJM4AR2 Freescale Semiconductor, MCIMX251AJM4AR2 Datasheet - Page 112

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MCIMX251AJM4AR2

Manufacturer Part Number
MCIMX251AJM4AR2
Description
Processors - Application Specialized IMX25 1.2 AUTO
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MCIMX251AJM4AR2

Core
ARM926EJ-S
Processor Series
MCIMX25
Maximum Clock Frequency
400 MHz
Instruction / Data Cache Memory
16 KB
Data Ram Size
128 KB
Operating Supply Voltage
1.15 V to 1.52 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
MAPBGA-400
Interface Type
USB
Memory Type
DDR2
Minimum Operating Temperature
- 40 C
assertion of soc is detected. Thus, if the soc signal is continuously asserted, the ADC undergoes successive
conversion cycles and achieves the maximum sampling rate. If soc is negated, no conversion is initiated.
The output data can be read from adcout11...adcout0, and is available tdata nanoseconds after the rising
edge of eoc. The reset signal and the digital signals controlling the analog switches (ypsw, xpsw, ynsw,
xnsw) are totally asynchronous.
The following conditions are necessary to guarantee the correct operation of the ADC:
112
The input multiplexer selection (selin11…selin0) is stable during both the last clock cycle (14
and the first clock cycle (1
selection during clock cycles 2 to 13.
The references are stable during clock cycle 1 to 13. The best way to guarantee this is to make the
reference multiplexer selection (selrefp and selrefn) before issuing an soc pulse and changing it
only after an eoc pulse has been acquired, during the last clock cycle (14).
i.MX25 Applications Processor for Automotive Products, Rev. 9
st
). The best way to guarantee this is to make the input multiplexer
Figure 82. Start-up Sequence
Freescale Semiconductor
th
)

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