MCIMX508CZK8B Freescale Semiconductor, MCIMX508CZK8B Datasheet - Page 71

• Manufacturer Part Number: MCIMX508CZK8B
• Description: Processors - Application Specialized CODEX REV 1.1
• Manufacturer: Freescale Semiconductor
• Type: Multimedia Applicationsr

Specifications of MCIMX508CZK8B

• Core: ARM Cortex A8
• Processor Series: i.MX50

4.8.4
DRAM Data input timing is defined for all DDR types: DDR2, LPDDR1, and LPDDR2.
Freescale Semiconductor
CK >= 200 MHz
DDR20
CK < 200 MHz
CK < 200 MHz
ID
DDR16
DDR15
DDR16
ID
DRAM Data Input Timing
Positive DQS latching edge to associated CK edge
DRAM_SDCLK_B
DRAM_SDCLK
DRAM_SDQS_B
DRAM_SDQS
DRAM_D
The DDR15,16 could be adjusted by the parameter “DLL_WR_DELAY”;
The ideal case is that SDQS is center aligned to the DRAM_D data valid
window;
For this table, HW_DRAM_PHY15[14:8] (DLL_WR_DELAY) = 0x10;
DQ & DQM output hold time relative to DQS
DQ & DQM output setup time relative to DQS
DQ & DQM output hold time relative to DQS
i.MX50 Applications Processors for Consumer Products, Rev. 4
Description
Figure 31. DRAM Data Input Timing
Description
Table 46. DDR Output AC Timing
Table 47. DDR2 Input AC Timing
DDR20
DDR21
NOTE
d0
tDQSCK
Symbol
DDR22
d1
Symbol
tDH
tDS
tDH
d2
-0.5 tCK
d3
0.5 tCK
Min
- 1.3
Min
1
1
Electrical Characteristics
Max
Max
—
—
—
—
Unit
Unit
ns
ns
ns
ns
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