MCIMX6S4AVM08ABR Freescale Semiconductor, MCIMX6S4AVM08ABR Datasheet - Page 173

• Manufacturer Part Number: MCIMX6S4AVM08ABR
• Description: Processors - Application Specialized i.MX6 Solo rev 1.1
• Manufacturer: Freescale Semiconductor
• Type: Multimedia Applicationsr

Specifications of MCIMX6S4AVM08ABR

• Rohs: yes
• Core: ARM Cortex A9
• Processor Series: i.MX6
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 800 MHz
• Data Ram Size: 16 KB
• Operating Supply Voltage: 1.175 V to 1.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: MAPBGA-624
• Interface Type: Parallel
• Memory Type: L1/L2 Cache, ROM, SRAM
• Minimum Operating Temperature: - 40 C
• Number Of Timers: 2

7
Table 104
Freescale Semiconductor
Number
Rev. 1
Rev. 0
Rev.
Revision History
11/2012 • Updated
10/2012 Initial public release.
provides a revision history for this datasheet.
Date
i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 1
Table 104. i.MX 6Solo/6DualLite Datasheet Document Revision History
• Updated
• In
• In
• Updated
• In
• Updated
• Updated
• Updated
• In
• Updated
• In
• In
• Updated
• Updated
• Updated
• Updated
• In
• Updated
• Updated
• Updated
of 1 Gbps ENET.
column, changed DSZ value to “001.”
Section 1.2, “Features,”
Table 7, "Absolute Maximum Ratings," on page
Table 10, "On-Chip LDOs and their On-Chip Loads," on page
Table 23, "OSC32K Main Characteristics," on page
Table 42, "EIM Internal Module Multiplexing," on page
Table 54, "ECSPI Master Mode Timing Parameters," on page
Table 76, "Electrical and Timing Information," on page
Table 1, "Orderable Part Numbers," on page
Figure 1, "Part Number Nomenclature—i.MX 6DualLite and 6Solo," on page
Table 9, "Operating Ranges," on page
Table 12, "Maximal Supply Currents," on page
Table 15, "PCIe PHY Current Drain," on page
Table 16, "HDMI PHY Current Drain," on page
Table 27, "LVDS I/O DC Characteristics," on page
Table 64, "RMII Signal Timing," on page
Section 4.11.5.3, “RGMII Signal Switching Specifications.”
Section 4.11.6, “Flexible Controller Area Network (FLEXCAN) AC Electrical Specifications.”
Table 64, "RMII Signal Timing," on page
Figure 88, "PWM Timing," on page
Table 83, "PWM Output Timing Parameters," on page
Section 4.11.22, “USB PHY Parameters.”
added a footnote on the bottom of page 6 to specify performance limitation
Substantive Change(s)
127.
24.
91.
91.
22, added details of VDD_SNVS_IN parameter.
36, added 100 kΩ as ESR parameter max value.
3.
30.
27.
31.
51, Multiplexed Address/Data mode, 16 Bit
116, updated ΔV
41.
127.
25, removed VDD_CACHE_CAP load.
78, updated CS5 and CS6 min values.
CMTX(LF)
max value.
Revision History
4.
173