MCIMX6S4AVM08ABR Freescale Semiconductor, MCIMX6S4AVM08ABR Datasheet - Page 15

• Manufacturer Part Number: MCIMX6S4AVM08ABR
• Description: Processors - Application Specialized i.MX6 Solo rev 1.1
• Manufacturer: Freescale Semiconductor
• Type: Multimedia Applicationsr

Specifications of MCIMX6S4AVM08ABR

• Rohs: yes
• Core: ARM Cortex A9
• Processor Series: i.MX6
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 800 MHz
• Data Ram Size: 16 KB
• Operating Supply Voltage: 1.175 V to 1.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: MAPBGA-624
• Interface Type: Parallel
• Memory Type: L1/L2 Cache, ROM, SRAM
• Minimum Operating Temperature: - 40 C
• Number Of Timers: 2

Freescale Semiconductor
Block Mnemonic
OCOTP_CTRL
OSC32KHz
OCRAM
ROMCP
PWM-1
PWM-2
PWM-3
PWM-4
128 KB
16 KB
96KB
ROM
PCIe
PMU
RAM
RAM
i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 1
Secure/non-secure RAM
Pulse Width Modulation
Power-Management
ROM Controller with
On-Chip Memory
PCI Express 2.0
OTP Controller
Internal RAM
Block Name
OSC32KHz
Boot ROM
controller
functions
Patch
Table 2. i.MX 6Solo/6DualLite Modules List (continued)
Secured Internal
Internal Memory
Internal Memory
Subsystem
Connectivity
Connectivity
Peripherals
Peripherals
Data Path
Data Path
Data Path
Clocking
Security
Memory
The On-Chip OTP controller (OCOTP_CTRL) provides
an interface for reading, programming, and/or overriding
identification and control information stored in on-chip
fuse elements. The module supports
electrically-programmable poly fuses (eFUSEs). The
OCOTP_CTRL also provides a set of volatile
software-accessible signals that can be used for
software control of hardware elements, not requiring
non-volatility. The OCOTP_CTRL provides the primary
user-visible mechanism for interfacing with on-chip fuse
elements. Among the uses for the fuses are unique chip
identifiers, mask revision numbers, cryptographic keys,
JTAG secure mode, boot characteristics, and various
control signals, requiring permanent non-volatility.
The On-Chip Memory controller (OCRAM) module is
designed as an interface between system’s AXI bus and
internal (on-chip) SRAM memory module.
In i.MX 6Solo/6DualLite processors, the OCRAM is
used for controlling the 128 KB multimedia RAM through
a 64-bit AXI bus.
Generates 32.768 KHz clock from external crystal.
The PCIe IP provides PCI Express Gen 2.0 functionality.
Integrated power management unit. Used to provide
power to various SoC domains.
The pulse-width modulator (PWM) has a 16-bit counter
and is optimized to generate sound from stored sample
audio images and it can also generate tones. It uses
16-bit resolution and a 4x16 data FIFO to generate
sound.
Internal RAM, which is accessed through OCRAM
memory controller.
Secure/non-secure Internal RAM, interfaced through
the CAAM.
Supports secure and regular Boot Modes. Includes read
protection on 4K region for content protection.
ROM Controller with ROM Patch support
Brief Description
Modules List
15