MCIMX6Q4AVT08AC Freescale Semiconductor, MCIMX6Q4AVT08AC Datasheet - Page 132

• Manufacturer Part Number: MCIMX6Q4AVT08AC
• Description: Processors - Application Specialized i.MX6Q
• Manufacturer: Freescale Semiconductor
• Type: Multimedia Applicationsr

Specifications of MCIMX6Q4AVT08AC

• Rohs: yes
• Core: ARM Cortex A9
• Processor Series: i.MX6
• Data Bus Width: 32 bit
• Operating Supply Voltage: 1.05 V to 1.5 V
• Memory Type: L1/L2 Cache, ROM, SRAM

Electrical Characteristics
4.11.20.4 SSI Receiver Timing with External Clock
Figure 99
receiver timing with the external clock.
132
SS44
SS45
SS46
ID
depicts the SSI receiver external clock timing and
AUDx_RXD setup before AUDx_TXC falling
AUDx_RXD hold after AUDx_TXC falling
AUDx_RXD rise/fall time
AUDx_TXFS (bl)
AUDx_TXFS (wl)
•
•
•
•
•
i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2
AUDx_RXD
AUDx_TXC
All the timings for the SSI are given for a non-inverted serial clock
polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync
(TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have
been inverted, all the timing remains valid by inverting the clock signal
AUDx_TXC/AUDx_RXC and/or the frame sync
AUDx_TXFS/AUDx_RXFS shown in the tables and in the figures.
All timings are on Audiomux Pads when SSI is being used for data
transfer.
AUDx_TXC and AUDx_RXC refer to the Transmit and Receive
sections of the SSI.
The terms WL and BL refer to Word Length (WL) and Bit Length (BL).
For internal Frame Sync operation using external clock, the frame sync
timing is same as that of transmit data (for example, during AC97 mode
of operation).
Table 89. SSI Transmitter Timing with External Clock (continued)
(Input)
(Input)
(Input)
(Input)
Figure 99. SSI Receiver External Clock Timing Diagram
SS23
SS28
Parameter
Synchronous External Clock Operation
SS22
SS32
SS35
SS30
NOTE
SS40
SS25
SS26
Table 90
SS41
10.0
Min
lists the timing parameters for the
2.0
—
SS24
SS36
Freescale Semiconductor
Max
6.0
—
—
SS34
Unit
ns
ns
ns