MCIMX6Q4AVT08AC Freescale Semiconductor, MCIMX6Q4AVT08AC Datasheet - Page 125

• Manufacturer Part Number: MCIMX6Q4AVT08AC
• Description: Processors - Application Specialized i.MX6Q
• Manufacturer: Freescale Semiconductor
• Type: Multimedia Applicationsr

Specifications of MCIMX6Q4AVT08AC

• Rohs: yes
• Core: ARM Cortex A9
• Processor Series: i.MX6
• Data Bus Width: 32 bit
• Operating Supply Voltage: 1.05 V to 1.5 V
• Memory Type: L1/L2 Cache, ROM, SRAM

4.11.19 SPDIF Timing Parameters
The Sony/Philips Digital Interconnect Format (SPDIF) data is sent using the bi-phase marking code. When
encoding, the SPDIF data signal is modulated by a clock that is twice the bit rate of the data signal.
Table 85
Interconnect Format (SPDIF), including the timing of the modulating Rx clock (SPDIF_SR_CLK) for
SPDIF in Rx mode and the timing of the modulating Tx clock (SPDIF_ST_CLK) for SPDIF in Tx mode.
Freescale Semiconductor
1
2
JTAG_TRST_B
T
V
DC
M
SJ10
SJ11
SJ12
SJ13
SJ0
SJ1
SJ2
SJ3
SJ4
SJ5
SJ6
SJ7
SJ8
SJ9
and
ID
= mid-point voltage
JTAG_TCK
= target frequency of SJC
Figure 94
(Input)
(Input)
JTAG_TCK frequency of operation 1/(3xT
JTAG_TCK cycle time in crystal mode
JTAG_TCK clock pulse width measured at
JTAG_TCK rise and fall times
Boundary scan input data set-up time
Boundary scan input data hold time
JTAG_TCK low to output data valid
JTAG_TCK low to output high impedance
JTAG_TMS, JTAG_TDI data set-up time
JTAG_TMS, JTAG_TDI data hold time
JTAG_TCK low to JTAG_TDO data valid
JTAG_TCK low to JTAG_TDO high impedance
JTAG_TRST_B assert time
JTAG_TRST_B set-up time to JTAG_TCK low
i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2
and
Figure 95
SJ12
Figure 93. JTAG_TRST_B Timing Diagram
SJ13
Parameter
show SPDIF timing parameters for the Sony/Philips Digital
Table 84. JTAG Timing
1,2
DC
V
)
M
1
2
0.001
22.5
Min
100
45
—
24
25
—
—
40
—
—
5
5
All Frequencies
Electrical Characteristics
Max
22
40
40
44
44
—
—
—
—
—
—
—
—
3
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
125