P5020NSE1VNB Freescale Semiconductor, P5020NSE1VNB Datasheet - Page 76

• Manufacturer Part Number: P5020NSE1VNB
• Description: Processors - Application Specialized Std Tmp Enc2000/1333
• Manufacturer: Freescale Semiconductor

Specifications of P5020NSE1VNB

• Rohs: yes

Electrical Characteristics
76
For recommended operating conditions, see
MDQ/MECC/MDM output hold with respect to
MDQS
1333 MT/s data rate
1200 MT/s data rate
1066 MT/s data rate
800 MT/s data rate
MDQS preamble
MDQS postamble
Note:
6. Note that for data rates of 1200 MT/s or higher, it is required to program the start value of the DQS adjust for write leveling.
1. The symbols used for timing specifications follow the pattern of t
2. All MCK/MCK and MDQS/MDQS referenced measurements are made from the crossing of the two signals.
3. ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK, MCS, and MDQ/MECC/MDM/MDQS.
4. Note that t
5. Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ), ECC
inputs and t
(DD) from the rising or falling edge of the reference clock (KH or KL) until the output went invalid (AX or DX). For example,
t
(A) are setup (S) or output valid time. Also, t
(K) goes low (L) until data outputs (D) are invalid (X) or data output hold time.
(DD) from the rising edge of the MCK[n] clock (KH) until the MDQS signal is valid (MH). t
control of the MDQS override bits (called WR_DATA_DELAY) in the TIMING_CFG_2 register. This is typically set to the
same delay as in DDR_SDRAM_CLK_CNTL[CLK_ADJUST]. The timing parameters listed in the table assume that these
two parameters have been set to the same adjustment value. See the reference manual for your chip for a description and
explanation of the timing modifications enabled by use of these bits.
(MECC), or data mask (MDM). The data strobe must be centered inside of the data eye at the pins of the microprocessor.
DDKHAS
Table 27. DDR3 and DDR3L SDRAM Interface Output AC Timing Specifications (continued)
symbolizes DDR timing (DD) for the time t
DDKHMH
(first two letters of functional block)(reference)(state)(signal)(state)
For the ADDR/CMD setup and hold specifications in
control register is set to adjust the memory clocks by ½ applied cycle.
Parameter
follows the symbol conventions described in note 1. For example, t
P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0
Table
3.
DDKLDX
Symbol
t
t
t
t
DDKHDX,
DDKHMP
DDKHME
DDKLDX
MCK
symbolizes DDR timing (DD) for the time t
1
memory clock reference (K) goes from the high (H) state until outputs
NOTE
0.9 × t
0.4 × t
(first two letters of functional block)(signal)(state) (reference)(state)
for outputs. Output hold time can be read as DDR timing
Min
250
275
300
375
Table
MCK
MCK
27, it is assumed that the clock
0.6 × t
DDKHMH
Max
DDKHMH
—
—
—
—
—
MCK
MCK
describes the DDR timing
Freescale Semiconductor
can be modified through
memory clock reference
Unit
ps
ns
ns
Note
—
—
5
for