MCIMX6D7CVT08AC Freescale Semiconductor, MCIMX6D7CVT08AC Datasheet - Page 95

• Manufacturer Part Number: MCIMX6D7CVT08AC
• Description: Processors - Application Specialized i.MX6D
• Manufacturer: Freescale Semiconductor
• Type: Multimedia Applicationsr

Specifications of MCIMX6D7CVT08AC

• Rohs: yes
• Core: ARM Cortex A9
• Processor Series: i.MX6
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 800 MHz
• Data Ram Size: 16 KB
• Maximum Operating Temperature: + 105
• Mounting Style: SMD/SMT
• Package / Case: FCBGA
• Interface Type: I2C, I2S, UART, USB
• Memory Type: L1/L2 Cache, ROM, SRAM
• Minimum Operating Temperature: - 40 C
• Number Of Timers: 2

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4.11.10.2 Sensor Interface Timings
There are three camera timing modes supported by the IPU.
4.11.10.2.1 BT.656 and BT.1120 Video Mode
Smart camera sensors, which include imaging processing, usually support video mode transfer. They use
an embedded timing syntax to replace the IPU2_CSIx_VSYNC and IPU2_CSIx_HSYNC signals. The
timing syntax is defined by the BT.656/BT.1120 standards.
This operation mode follows the recommendations of ITU BT.656/ ITU BT.1120 specifications. The only
control signal used is IPU2_CSIx_PIX_CLK. Start-of-frame and active-line signals are embedded in the
data stream. An active line starts with a SAV code and ends with a EAV code. In some cases, digital
blanking is inserted in between EAV and SAV code. The CSI decodes and filters out the timing-coding
from the data stream, thus recovering IPU2_CSIx_VSYNC and IPU2_CSIx_HSYNC signals for internal
use. On BT.656 one component per cycle is received over the IPU2_CSIx_DATA_EN bus. On BT.1120
two components per cycle are received over the IPU2_CSIx_DATA_EN bus.
4.11.10.2.2 Gated Clock Mode
The IPU2_CSIx_VSYNC, IPU2_CSIx_HSYNC, and IPU2_CSIx_PIX_CLK signals are used in this
mode. See
Freescale Semiconductor
The MSB bits are duplicated on LSB bits implementing color extension.
The two MSB bits are duplicated on LSB bits implementing color extension.
YCbCr, 8 bits—Supported within the BT.656 protocol (sync embedded within the data stream).
RGB, 16 bits—Supported in two ways: (1) As a “generic data” input—with no on-the-fly processing; (2) With on-the-fly
processing, but only under some restrictions on the control protocol.
YCbCr, 16 bits—Supported as a “generic-data” input—with no on-the-fly processing.
YCbCr, 16 bits—Supported as a sub-case of the YCbCr, 20 bits, under the same conditions (BT.1120 protocol).
YCbCr, 20 bits—Supported only within the BT.1120 protocol (syncs embedded within the data stream).
Figure
63.
i.MX 6Dual/6Quad Applications Processors for Industrial Products, Rev. 2
Figure 63. Gated Clock Mode Timing Diagram
Electrical Characteristics
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