MCIMX6U5EVM10AB Freescale Semiconductor, MCIMX6U5EVM10AB Datasheet - Page 166

• Manufacturer Part Number: MCIMX6U5EVM10AB
• Description: Processors - Application Specialized i.MX6 DualLite
• Manufacturer: Freescale Semiconductor
• Type: Multimedia Applicationsr

Specifications of MCIMX6U5EVM10AB

• Rohs: yes
• Core: ARM Cortex A9
• Processor Series: i.MX6
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 1 GHz
• Data Ram Size: 128 KB
• Operating Supply Voltage: 1.175 V to 1.5 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Package / Case: MAPBGA-624
• Interface Type: I2C, I2S, UART, USB
• Memory Type: L1/L2 Cache, ROM, SRAM
• Minimum Operating Temperature: - 20 C
• Number Of Timers: 2

Revision History
7
Table 95
166
Number
Rev. 1
Rev. 0
Rev.
Revision History
provides a revision history for this datasheet.
11/2012 • Updated
10/2012 Initial public release.
Date
i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 1
Table 95. i.MX 6Solo/6DualLite Datasheet Document Revision History
• In
• In
• Updated
• In
• Updated
• Updated
• Updated
• In
• Updated
• In
• In
• Updated
• Updated
• Added
• Updated
• In
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of 1 Gbps ENET.
column, changed DSZ value to “001.”
Section 1.2, “Features,”
Table 7, "Absolute Maximum Ratings," on page
Table 10, "On-Chip LDOs and their On-Chip Loads," on page
Table 22, "OSC32K Main Characteristics," on page
Table 38, "EIM Internal Module Multiplexing," on page
Table 50, "ECSPI Master Mode Timing Parameters," on page
Table 72, "Electrical and Timing Information," on page
Section 4.11.6, “Flexible Controller Area Network (FLEXCAN) AC Electrical Specifications.”
Figure 1, "Part Number Nomenclature—i.MX 6DualLite and 6Solo," on page
Table 9, "Operating Ranges," on page
Table 12, "Maximal Supply Currents," on page
Table 15, "PCIe PHY Current Drain," on page
Table 16, "HDMI PHY Current Drain," on page
Table 26, "LVDS I/O DC Characteristics," on page
Table 60, "RMII Signal Timing," on page
Section 4.11.5.3, “RGMII Signal Switching Specifications.”
Table 60, "RMII Signal Timing," on page
Figure 84, "PWM Timing," on page
Table 74, "PWM Output Timing Parameters," on page
Section 4.11.21, “USB PHY Parameters.”
added a footnote on the bottom of page 6 to specify performance limitation
Substantive Change(s)
120.
24.
89.
89.
22, added details of VDD_SNVS_IN parameter.
36, added 100 kΩ as ESR parameter max value.
30.
27.
31.
49, Multiplexed Address/Data mode, 16 Bit
114, updated ΔV
40.
120.
25, removed VDD_CACHE_CAP load.
76, updated CS5 and CS6 min values.
CMTX(LF)
Freescale Semiconductor
max value.
4.