AT24C1024B-TH25-B Atmel, AT24C1024B-TH25-B Datasheet - Page 6
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AT24C1024B-TH25-B
Manufacturer Part Number
AT24C1024B-TH25-B
Description
IC EEPROM 1MBIT 1MHZ 8TSSOP
Manufacturer
Atmel
Datasheet
1.AT24C1024BN-SH25-B.pdf
(25 pages)
Specifications of AT24C1024B-TH25-B
Format - Memory
EEPROMs - Serial
Memory Type
EEPROM
Memory Size
1M (128K x 8)
Speed
1MHz
Interface
I²C, 2-Wire Serial
Voltage - Supply
2.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-TSSOP
Organization
128 K x 8
Interface Type
2-Wire
Maximum Clock Frequency
1 MHz
Access Time
550 ns
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2.5 V
Maximum Operating Current
3 mA
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Operating Supply Voltage
3.3 V, 5 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Figure 4-1.
Figure 4-2.
6
SCL
SDA
SDA OUT
SDA IN
AT24C1024B
SCL
Software Reset
Bus Timing (SCL: Serial Clock, SDA: Serial Data I/O
Start bit
t
SU.STA
START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which
must precede any other command (see
STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a
read sequence, the Stop command will place the EEPROM in a standby power mode (see
ure 4-5 on page
ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the
EEPROM in 8-bit words. The EEPROM sends a zero during the ninth clock cycle to acknowl-
edge that it has received each word.
STANDBY MODE: The AT24C1024B features a low-power standby mode which is enabled: a)
upon power-up and b) after the receipt of the stop bit and the completion of any internal
operations.
SOFTWARE RESET: After an interruption in protocol, power loss or system reset, any 2-wire
part can be protocol reset by following these steps: (a) Create a start bit condition, (b) clock 9
cycles, (c) create another start bit followed by stop bit condition as shown below. The device is
ready for next communication after above steps have been completed.
1
t
HD.STA
2
t
t
F
LOW
8).
t
AA
Dummy Clock Cycles
3
t
HIGH
t
HD.DAT
t
Figure 4-5 on page
LOW
®
)
8
t
t
SU.DAT
DH
9
8).
Start bit
t
R
t
SU.STO
5194F–SEEPR–1/08
Stop bit
t
BUF
Fig-