MAX1366ECM-T Maxim Integrated, MAX1366ECM-T Datasheet - Page 10

• Manufacturer Part Number: MAX1366ECM-T
• Description: LED Display Drivers
• Manufacturer: Maxim Integrated

Specifications of MAX1366ECM-T

• Mounting Style: SMD/SMT
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C

Microcontroller-Interface, 4.5-/3.5-Digit Panel
Meters with 4–20mA Output
10
PIN
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10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
1
2
3
4
5
6
7
8
9
DACDATA_SEL
REG_FORCE
GND_DAC
DACVOUT
REG_VDD
REG_AMP
DAC_VDD
REF_DAC
CONV_IN
4–20OUT
REFSELE
GND_V/I
EN_BPM
CS_DAC
NAME
DV
AV
AIN+
GND
CMP
EN_I
EOC
AIN-
CLK
SET
DD
DD
Positive Analog Input. Positive side of fully differential analog input. Bypass AIN+ to GND with a
0.1µF or greater capacitor.
Negative Analog Input. Negative side of fully differential analog input. Bypass AIN- to GND with a
0.1µF or greater capacitor.
Ground. Connect to star ground.
Analog Positive Supply Voltage. Connect AV
to GND with a 0.1µF capacitor.
Digital Positive Supply Voltage. Connect DV
to GND with a 0.1µF capacitor.
Segment Current Set. Connect to ground through a resistor to set the segment current. See Table
7 for segment-current selection.
V/I Converter Regulated Supply Output. REG_ VDD is typically 2.5V.
REG_VDD Control. Drives the gate of external depletion mode FET.
Regulator/Reference Buffer Supply. Connect to a 4.75V to 5.25V power supply.
Regulator Compensation Node. Connect a 0.1µF capacitor from CMP to REG_FORCE.
DAC Analog Supply. Connect DAC_VDD to a +2.7V to +5.25V power supply.
DAC Voltage Output. DAC output impedance is typically 6.2kΩ.
V/I Converter Input
4–20mA (0 to 16mA) Current-Loop Output. Referenced to GND.
DAC Analog Ground. Connect to star ground.
V/I Converter Analog Ground. Connect to star ground.
V-to-I Converter/DAC Reference Input. Connect a voltage source for external reference operation
or leave floating for internal reference. Bypass REF_DAC with a 0.1µF capacitor to GND for either
internal or external reference operation.
Acti ve- H i g h V /I- C onver ter Bi p ol ar - M od e E nab l e. S et hi g h for b i p ol ar m od e. S et l ow for uni p ol ar m od e.
Acti ve- H i g h V /I- C onver ter 4m A O ffset E nab l e. S et l ow for 0 to 16m A outp ut. S et hi g h for 4–20m A
DAC External Reference Selection. Set low for internal reference. Set high for external reference.
Leave REF_DAC unconnected when REFSELE is low.
DAC Data-Source Select. Set high to select DAC register. Set low to have the DAC follow the ADC
output.
DAC SPI Chip Select. See Table 8.
External Clock Input. When the EXTCLK register bit is set to one, CLK is the master clock input for
the modulator, filter, and DAC. When the EXTCLK register bit is reset to zero, the internal clock is
used. The default power-on state is EXTCLK = 0 (internal clock mode). Connect CLK to GND or
DV
Active-Low End-of-Conversion Logic Output. A logic-low at EOC indicates that a new ADC result is
available in the ADC result register.
DD
when using internal clock.
FUNCTION
DD
DD
to a +2.7V to +5.25V power supply. Bypass DV
to a +2.7V to +5.25V power supply. Bypass AV
Pin Description
DD
DD