11AA010-I/P Microchip Technology, 11AA010-I/P Datasheet - Page 6
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11AA010-I/P
Manufacturer Part Number
11AA010-I/P
Description
IC EEPROM 1KBIT 100KHZ 8DIP
Manufacturer
Microchip Technology
Specifications of 11AA010-I/P
Memory Size
1K (128 x 8)
Package / Case
8-DIP (0.300", 7.62mm)
Operating Temperature
-40°C ~ 85°C
Format - Memory
EEPROMs - Serial
Memory Type
EEPROM
Speed
100kHz
Interface
UNI/O™ (Single Wire)
Voltage - Supply
1.8 V ~ 5.5 V
Organization
128 x 8
Interface Type
Serial
Maximum Clock Frequency
100 KHz
Supply Voltage (max)
5.5 V
Supply Voltage (min)
1.8 V
Maximum Operating Current
50 uA
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
Minimum Operating Temperature
- 40 C
Operating Supply Voltage
1.8 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
11AA010-I/P
Manufacturer:
MICROCHIP
Quantity:
12 000
11AAXXX/11LCXXX
2.0
2.1
The 11XX family of serial EEPROMs support the
UNI/O
controllers, including Microchip’s PIC
trollers, ASICs, or any other device with an available
discrete I/O line that can be configured properly to
match the UNI/O protocol.
The 11XX devices contain an 8-bit instruction register.
The devices are accessed via the SCIO pin.
Table 4-1 contains a list of the possible instruction
bytes and format for device operation. All instructions,
addresses, and data are transferred MSb first, LSb
last.
Data is embedded into the I/O stream through Man-
chester encoding. The bus is controlled by a master
device which determines the clock period, controls the
bus access and initiates all operations, while the 11XX
works as slave. Both master and slave can operate as
transmitter or receiver, but the master device deter-
mines which mode is active.
FIGURE 2-1:
DS22067D-page 6
SCIO
™
I/O Control
Current-
Limited
Control
protocol. They can be interfaced with micro-
STATUS
FUNCTIONAL DESCRIPTION
Principles of Operation
Register
Slope
Logic
Vcc
Vss
Memory
BLOCK DIAGRAM
Control
Logic
Dec
X
Y Decoder
Sense Amp.
R/W Control
Page Latches
HV Generator
®
EEPROM
Array
microcon-
Preliminary
© 2008 Microchip Technology Inc.