XRT7295A/98ES-DS3 Exar, XRT7295A/98ES-DS3 Datasheet - Page 9

• Manufacturer Part Number: XRT7295A/98ES-DS3
• Description: Peripheral Drivers & Components - PCIs comeswith XRT7295A
• Manufacturer: Exar

Specifications of XRT7295A/98ES-DS3

• Product Category: Peripheral Drivers & Components - PCIs
• Rohs: yes

False-Lock Immunity
False-lock is defined as the condition where a PLL
recovered clock obtains stable phase-lock at a fre-
quency not equal to the incoming data rate. The
XRT7295AE uses a combination frequency/phase-
lock architecture to prevent false-lock. An on-chip
frequency comparator continuously compares the
EXCLK reference to the PLL clock. If the frequency
difference between the EXCLK and PLL clock exceeds
approximately +/-0.5% of EXCLK, correction circuitry
acts to force the reacquisition of the proper frequency
and phase.
Acquisition Time
If a valid input signal is assumed to be already present
at RIN, the maximum time between the application of
device power and error-free operation is 20ms. If power
has already been applied, the interval between the
application of valid data and error-free operation is 4ns.
Loss-of-Lock Indication
As previously stated, the PLL acquisition aid circuitry
monitors the PLL clock frequency relative to the
EXCLK frequency.
The acquisition circuit also monitors the resumed data
to detect possible phase-lock which is 180° out of a
normal phase alignment. The RLOL alarm is activated
if either or both of the following conditions exist:
A high RLOL output indicates that the acquisition
circuit is working to bring the PLL into proper frequency
lock. RLOL remains high until frequency lock has
occurred; however, the minimum RLOL pulse width is
32 clock cycles.
Loss-of-Signal Detection
Figure 1 shows that analog and digital methods of loss-
of-signal (LOS) detection are combined to create the
RLOS alarm output. RLOS is set if either the analog or
digital detection circuitry indicates LOS has occurred.
- The difference between the PLL clock and the
- The retimed data is 180° out of a normal phase
EXCLK frequency exceeds approximately +/-
0.5%.
alignment.
Rev. 2.0.0
9
two 50k +/-10% resistor as a voltage divider between
V
Notes:
1
2
Analog Detection
The analog LOS detector monitors the peak input
signal amplitude. RLOS makes a high-to-low transition
(input signal regained) when the input signal amplitude
exceeds the loss-of-signal threshold defined in Table
4. The RLOS low-to-high transition (input signal loss)
occurs at a level typically 1.0dB below the high-to-low
transition level. The hysteresis prevents RLOS chat-
tering. Once set, the RLOS alarm remains high for at
least 32 clock cycles, allowing for system detection of
a LOS condition without the use of an external alarm
latch.
To allow for varying levels of noise and crosstalk in
different applications, three loss-of-signal threshold
settings are available using the LOSTHR pin. Setting
LOSTHR = V
threshold; LOSTHR = V
LOSTHR = GND provides the highest threshold. The
LOSTHR pin must be set to its desired value at power
up and must not be changed during operation.
34.368
Mbps
Data
Rate
DD
E3
D and GNDD) provides an intermediate threshold.
The RLOS alarm is an indication of the presence of an
input signal, not a bit error rate indication. Table 1
gives the minimum input amplitude needed for error-
free operation (BER<1E
state, the device will attempt to recover correct timing
and data.
The RLOS low-to-high transition typically occurs 1dB
below the high-to-low transition.
REQB LOSTHR MIN
0
1
DD
provides the lowest loss-of-signal
V
V
V
V
DD
DD
XRT7295AE
0
0
DD
DD
/2
/2
DD
/2 (can be produced using
-9
). Independent of the RLOS
60
40
25
45
30
20
Threshold
Max
220
145
175
115
90
70
mV pk
mV pk
mV pk
mV pk
mV pk
mV pk
Unit