XRT7295A/98ES-DS3 Exar, XRT7295A/98ES-DS3 Datasheet
XRT7295A/98ES-DS3
Specifications of XRT7295A/98ES-DS3
Related parts for XRT7295A/98ES-DS3
XRT7295A/98ES-DS3 Summary of contents
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... The on-chip equalizer is designed for cable ORDERING INFORMATION Part No. XRT7295AEIW Rev. 2.0.0 EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 APPLICATIONS l Interface to E3 Networks l CSU/DSU Equipment l PCM Test Equipment ...
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XRT7295AE PIN CONFIGURATION Rev. 2.0.0 Figure 1. Block Diagram 2 ...
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PIN DESCRIPTION Pin # Symbol Type 1 GNDA 3,6 TMC1-TMC2 I 4,5 LPF-1-LPF RLOS O 8 RLOL O 9 GNDD 10 GNDC EXCLK I 14 ...
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XRT7295AE DC ELECTRICAL CHARACTERISTICS Test Conditions: -40 ° C < TA < +85 ° C, VDD = 5V +/-10% Typical values are for V =5.0V, 25 ° C, and random data. Maximum values for data. Symbol Parameter ...
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XRT7295AE XRT7296 Transmitter SYSTEM DESCRIPTION Receive Path Configurations The diagram in Figure 2 shows a typical system application for the XRT7295AE. In the receive signal path (see Figure 1), the internal equalizer can be included by setting REQB=0 or bypass ...
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XRT7295AE Line Termination and Input Capacitance The recommended receive termination is shown in Figure 3. The 75 resistor terminates the coaxial cable with its characteristic impedance. The 0.01 F capaci- tor to R couples the signal into the receive input ...
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PLL bandwidth, which in turn is a function of the input 1s density. For higher 1s densities, the amount of gener- ated jitter decreases. Generated jitter also depends on the quality of ...
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XRT7295AE Jitter Transfer Characteristic The jitter transfer characteristic indicates the fraction of input jitter that reaches the RCLK output as a function of input jitter frequency. Table 3 shows impor- tant jitter transfer characteristic parameters. Figure 6 also shows a ...
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False-Lock Immunity False-lock is defined as the condition where a PLL recovered clock obtains stable phase-lock at a fre- quency not equal to the incoming data rate. The XRT7295AE uses a combination frequency/phase- lock architecture to prevent false-lock. An on-chip ...
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XRT7295AE Figure 7. Test Set-up for Interference Immunity Requirements Digital Detection In addition to the signal amplitude monitoring of the analog LOS detector, the digital LOS detector monitors the recovered data 1s density. The RLOS alarm goes high if 160 ...
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Note: 1 Recommended shield beads are the Fair-Rite 2643000101 or the Fair-Rite 2743019446 (surface mount). Figure 8. Recommended Power Supply Bypassing Network Rev. 2.0.0 XRT7295AE Receive Input The connections to the receive input pin, RIN, must be carefully considered. Noise-coupling ...
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XRT7295AE TIMING CHARACTERISTICS Test Conditions: All timing characteristics are measured with 10pF loading, -40°C < TA < 85° +/-10% DD Symbol tRCH1RCH2 Clock Rise Time (10%-90%) tRCL1RCL1 Clock Fall Time (10% to 90% TRCGRD Receive Propagation Delay ...
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XRT7295AE Figure 10. Evaluation System Schematic Rev. 2.0.0 XRT7295AE XRT7296 13 ...
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XRT7295AE Rev. 2.0.0 14 ...
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... EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user’ ...