24LC64T-I/SN Microchip Technology, 24LC64T-I/SN Datasheet - Page 11

• Manufacturer Part Number: 24LC64T-I/SN
• Description: IC EEPROM 64KBIT 400KHZ 8SOIC
• Manufacturer: Microchip Technology

Specifications of 24LC64T-I/SN

• Memory Size: 64K (8K x 8)
• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Speed: 400kHz
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• Memory Configuration: 8K X 8
• Ic Interface Type: I2C
• Clock Frequency: 400kHz
• Supply Voltage Range: 2.5V To 5.5V
• Memory Case Style: SOIC
• No. Of Pins: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 24LC64T-I/SN; 24LC64T-I/SNTR

8.0
Read operations are initiated in the same way as write
operations, with the exception that the R/W bit of the
control byte is set to one. There are three basic types
of read operations: current address read, random read
and sequential read.
8.1
The 24XX64 contains an address counter that main-
tains the address of the last word accessed, internally
incremented by one. Therefore, if the previous read
access was to address ‘n’ (n is any legal address), the
next current address read operation would access data
from address n + 1.
Upon receipt of the control byte with R/W bit set to one,
the 24XX64 issues an acknowledge and transmits the
eight-bit data word. The master will not acknowledge
the transfer, but does generate a Stop condition and the
24XX64 discontinues transmission (Figure 8-1).
8.2
Random read operations allow the master to access
any memory location in a random manner. To
perform this type of read operation, the word address
must first be set. This is accomplished by sending
the word address to the 24XX64 as part of a write
operation (R/W bit set to ‘0’). Once the word address
is sent, the master generates a Start condition
following the acknowledge.
FIGURE 8-1:
 2010 Microchip Technology Inc.
READ OPERATION
Current Address Read
Random Read
Bus Activity
Master
SDA Line
Bus Activity
CURRENT ADDRESS READ
S
T
A
R
T
S
Control
Byte
24AA64/24LC64/24FC64
This terminates the write operation, but not before
the internal Address Pointer is set. The master then
issues the control byte again, but with the R/W bit set
to a one. The 24XX64 will then issue an acknowl-
edge and transmit the 8-bit data word. The master
will not acknowledge the transfer, but does generate
a Stop condition, which causes the 24XX64 to
ter will point to the address location following the one
that was just read.
8.3
Sequential reads are initiated in the same way as
random reads, except that once the 24XX64 transmits
the first data byte, the master issues an acknowledge as
opposed to the Stop condition used in a random read.
This acknowledge directs the 24XX64 to transmit the
next sequentially-addressed 8-bit word (Figure 8-3).
Following the final byte being transmitted to the master,
the master will NOT generate an acknowledge, but will
generate a Stop condition. To provide sequential reads,
the 24XX64 contains an internal Address Pointer which
is incremented by one at the completion of each
operation. This Address Pointer allows the entire
memory contents to be serially read during one opera-
tion. The internal Address Pointer will automatically roll
over from address 1FFF to address 0000 if the master
acknowledges the byte received from the array address
1FFF.
discontinue
random Read command, the internal address coun-
A
C
K
Sequential Read
Data (n)
transmission
(Figure 8-2).
N
O
C
A
K
P
S
O
P
T
DS21189R-page 11
After
a