DS32506NW Maxim Integrated, DS32506NW Datasheet - Page 37

• Manufacturer Part Number: DS32506NW
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS32506NW

• Part # Aliases: 90-32506-NW0

Table 8-9. Pseudorandom Pattern Generation
Table 8-10. Repetitive Pattern Generation
After configuring these bits, the pattern must be loaded into the BERT. This is accomplished via a zero-to-one
transition on BERT.CR.TNPL for the pattern generator and BERT.CR.RNPL for the pattern detector. The BERT
must be enabled (PORT.CR3:BERTE = 1) before the pattern is loaded for the pattern load operation to take effect.
Monitoring the BERT requires reading the
Out of Synchronization (OOS) bit. The BEC bit is set to one when the bit error counter is one or more. The OOS bit
is set to one when the pattern detector is not synchronized to the incoming pattern, which occurs when it receives 6
or more bit errors within a 64-bit window. The Receive BERT Bit Count Register (BERT.RBCR) and the Receive
BERT Bit Error-Count Register (BERT.RBECR) are updated upon the reception of a Performance Monitor Update
signal (e.g., BERT.CR.LPMU). This signal updates the registers with the bit and bit-error counts since the last
update and then resets the counters. See Section
8.5.2 Receive Pattern Detection
The pattern detector synchronizes the receive pattern generator to the incoming pattern. The receive pattern
generator is a 32-bit shift register that shifts data from the least significant bit (LSB) or bit 1 to the most significant
bit (MSB) or bit 32. The input to bit 1 is the feedback. For a PRBS pattern (generating polynomial x
feedback is an XOR of bit n and bit y. For a repetitive pattern (length n), the feedback is bit n. The values for n and
y are individually programmable (1 to 32 with y < n) in the BERT.PCR:PLF and PTF fields. The output of the
receive pattern generator is the feedback. If QRSS is enabled (BERT.PCR:QRSS = 1), the feedback is forced to be
an XOR of bits 17 and 20, and the output is forced to one if the next 14 bits are all zeros. For PRBS and QRSS
patterns, the feedback is forced to one if bits 1 through 31 are all zeros. Depending on the type of pattern
programmed, pattern detection performs either PRBS synchronization or repetitive pattern synchronization.
2
2
O.153 (2047 type)
2
2
2
2
All 1s
All 0s
Alternating 1s and 0s
11001100...
3 in 24
1 in 16
1 in 8
1 in 4
9
11
15
20
20
23
-1 O.153 (511 type)
PATTERN TYPE
-1 O.152 and
-1 O.151
-1 O.153
-1 O.151 QRSS
-1 O.151
PATTERN TYPE
PTF[4:0]
PTF[4:0]
(hex)
(hex)
NA
NA
NA
NA
NA
NA
NA
NA
0D
04
08
10
02
11
BERT.PCR
BERT.PCR
PLF[4:0]
PLF[4:0]
BERT.SR
(hex)
(hex)
0A
0E
0F
08
13
13
16
00
00
01
03
17
07
03
REGISTER
REGISTER
8.7.4
37 of 130
register, which contains the Bit-Error Count (BEC) bit and the
PTS
PTS
0
0
0
0
0
0
1
1
1
1
1
1
1
1
for more details about performance monitor updates.
QRSS
QRSS
0
0
0
0
1
0
0
0
0
0
0
0
0
0
BERT.SPR2
BERT.SPR2
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFF20
DS32506/DS32508/DS32512
BERT.SPR1
BERT.SPR1
0xFFFC
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFE
0xFFFE
0xFF01
0xFFF1
0x0022
0x0001
n
+ x
BERT.CR
y
TPIC,
RPIC
+ 1), the
0
1
0
0
1
0