DS32508N-W Maxim Integrated, DS32508N-W Datasheet - Page 89
DS32508N-W
Manufacturer Part Number
DS32508N-W
Description
Network Controller & Processor ICs
Manufacturer
Maxim Integrated
Datasheet
1.DS32512W.pdf
(130 pages)
Specifications of DS32508N-W
Part # Aliases
90-32508-NW0
- Current page: 89 of 130
- Download datasheet (2Mb)
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bit 3: Performance Monitoring Update Status Interrupt Enable (PMSIE). This bit is the interrupt enable for the
BERT.SRL:PMSL status bit.
Bit 2: Bit Error Interrupt Enable (BEIE). This bit is the interrupt enable for the BERT.SRL:BEL status bit.
Bit 1: Bit Error Count Interrupt Enable (BECIE). This bit is the interrupt enable for the BERT.SRL:BECL status
bit.
Bit 0: Out of Synchronization Interrupt Enable (OOSIE). This bit is the interrupt enable for the BERT.SRL:OOSL
status bit.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bits 15 to 0: Bit Error Count (BEC[15:0])
0 = mask the interrupt
1 = enable the interrupt
0 = mask the interrupt
1 = enable the interrupt
0 = mask the interrupt
1 = enable the interrupt
0 = mask the interrupt
1 = enable the interrupt
15
15
—
—
0
7
0
0
7
0
14
14
—
—
0
6
0
0
6
0
BERT.SRIE
BERT Status Register Interrupt Enable
n * 80h + 60h
BERT.RBECR1
BERT Receive Bit Error Count Register #1
n * 80h + 64h
13
—
—
13
0
5
0
0
5
0
89 of 130
12
—
—
12
0
4
0
0
4
0
BEC[15:8]
BEC[7:0]
PMSIE
11
11
—
0
3
0
0
3
0
BEIE
10
10
—
0
2
0
0
2
0
DS32506/DS32508/DS32512
BECIE
—
9
0
1
0
9
0
1
0
OOSIE
—
8
0
0
0
8
0
0
0
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