DS32508N-W Maxim Integrated, DS32508N-W Datasheet - Page 75
DS32508N-W
Manufacturer Part Number
DS32508N-W
Description
Network Controller & Processor ICs
Manufacturer
Maxim Integrated
Datasheet
1.DS32512W.pdf
(130 pages)
Specifications of DS32508N-W
Part # Aliases
90-32508-NW0
- Current page: 75 of 130
- Download datasheet (2Mb)
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bit 10: Transmit Driver Monitor (TDM). This bit indicates when the transmit driver is faulty. See Section 8.2.9.
Bit 9: Transmit Output Failure (TFAIL). This bit indicates when there is a failure on the transmit differential
outputs (TXP/TXN). See Section 8.2.9.
Bit 8: Loss of Master Clock (LOMC). This bit indicates whether or not the master reference clock (DS3, E3, or
STS-1, depending on PORT.CR2:LM[1:0] setting) is available from the CLAD block. See Section 8.7.1.
Bit 4: Receive Preamp Status (RPAS). See Section 8.3.2.
Bit 3: Receive Failure Type 1 (RFAIL1). See Section 8.3.8.
Bit 2: Receive Failure Type 2 (RFAIL2). See Section 8.3.8.
Bit 1: Receive Loss of Lock (RLOL). See Section 8.3.4.
Bit 0: Analog Loss of Signal (ALOS). See Section 8.3.5.
0 = the transmit line driver is operating properly
1 = the transmit line driver is faulty
0 = an open or short has not been detected on TXP or TXN
1 = an open or short has been detected on TXP or TXN
0 = the master reference clock is present
1 = that master reference clock is not present
0 = the receiver preamp is off
1 = the receiver preamp is on
0 = a receive failure type 1 has not been detected on RXP or RXN
1 = a receive failure type 1 has been detected on RXP or RXN.
0 = a receive failure type 2 has not been detected on RXP or RXN
1 = a receive failure type 2 has been detected on RXP or RXN.
0 = the incoming clock frequency on RXP/RXN is within ± 7700ppm of the master reference clock
1 = the incoming clock frequency on RXP/RXN is more than ± 7900ppm away from the master
0 = an analog LOS (ALOS) condition has not been detected
1 = an ALOS condition has been detected
reference clock
15
—
—
0
7
1
14
—
—
0
6
1
LIU.SR
LIU Status Register
n * 80h + 28h
13
—
—
0
5
0
RPAS
75 of 130
12
—
0
4
0
RFAIL1
11
—
0
3
0
RFAIL2
TDM
10
0
2
0
DS32506/DS32508/DS32512
TFAIL
RLOL
9
0
1
0
LOMC
ALOS
8
0
0
0
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