DS32508-W Maxim Integrated, DS32508-W Datasheet - Page 54
![no-image](/images/no-image-200.jpg)
DS32508-W
Manufacturer Part Number
DS32508-W
Description
Network Controller & Processor ICs
Manufacturer
Maxim Integrated
Datasheet
1.DS32512W.pdf
(130 pages)
Specifications of DS32508-W
Part # Aliases
90-32508-W00
- Current page: 54 of 130
- Download datasheet (2Mb)
Bits 14 to 8: CLAD I/O Mode (CLAD[6:0]). These bits control the CLAD clock I/O pins REFCLK, CLKA, CLKB,
CLKC
Bit 5: CLKD Frequency is 19.44MHz (CLKD19). This bit specifies the frequency to be output on CLKD when the
CLAD[3] configuration bit is high.
Bit 4: INT Pin Mode (INTM). This bit determines the inactive mode of the
when an enabled interrupt source is active. See Section 8.10.
Bit 3: RDY/ACK Select (RAS). This bit controls the microprocessor interface output pin
(IFSEL = 100 or 110) and Motorola mode (IFSEL = 101 or 111).
Bit 2: RDY/ACK Disable (RAD). This bit disables the microprocessor interface output pin
Bit 1: Latched Status Bit Clear-on-Read Enable (LSBCRE). This bit determines when the latched status register
bits are cleared. See Section 8.8.5.
Bit 0: Global Write Mode (GWRM). This bit enables the global write mode. When this bit is set, a write to a
register of any port causes a write to the same register in all the ports. In this mode register reads are not
supported and result in undefined data. See Section 8.8.6.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
and CLKD. See
0 = 77.76MHz
1 = 19.44MHz
0 = Pin is high impedance when no enabled interrupts are active
1 = Pin drives high when no enabled interrupts are active
0 = Normal operation: RDY in Intel mode and ACK in Motorola mode
1 = Reverse operation: ACK in Intel mode and RDY in Motorola mode
0 = Enable, normal operation
1 = Disable, tri-state
0 = Latched status register bits are cleared on a write
1 = Latched status register bits are cleared on a read
0 = Normal write mode
1 = Global write mode
15
—
—
—
7
0
Table 8-11
14
—
0
0
6
and
GLOBAL.CR2
Global Control Register #2
004h
Table 8-12
CLKD19
13
0
5
0
in Section 8.7.1.
54 of 130
INTM
12
0
4
0
CLAD[6:0]
RAS
11
0
3
0
INT
pin. The
RAD
10
0
2
0
DS32506/DS32508/DS32512
INT
RDY/ACK
RDY/ACK
LSBCRE
pin always drives low
9
0
1
0
.
in Intel mode
GWRM
8
0
0
0
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