DS32512NW Maxim Integrated, DS32512NW Datasheet - Page 15
DS32512NW
Manufacturer Part Number
DS32512NW
Description
Network Controller & Processor ICs
Manufacturer
Maxim Integrated
Datasheet
1.DS32512W.pdf
(130 pages)
Specifications of DS32512NW
Part # Aliases
90-32512-NW0
- Current page: 15 of 130
- Download datasheet (2Mb)
A[0]/BSWAP
CLADBYP
RDY/ACK
REFCLK
JAD[1:0]
JAS[1:0]
WR/R/W
LBn[1:0]
GPIOAn
GPIOBn
GPIOAn
GPIOBn
RVDDn
A[10:1]
D[15:0]
VDD18
VDD33
JVDDn
JTCLK
JTRST
JVSSn
NAME
RD/DS
CPHA
CPOL
CLKC
CLKD
SCLK
CLKA
CLKB
JTMS
JTDO
RPD
SDO
JTDI
VSS
LBS
ALE
SDI
INT
INT
CS
CS
TYPE
I/Opd
I/Opd
I/Opd
I/Opd
Ipd
Ipd
Ipd
Ipd
I/O
Oz
Oz
Oz
I/O
I/O
I/O
Oz
I
I
I
O
O
PU
PU
PU
P
P
P
P
P
P
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
POWER SUPPLY AND GROUND PINS
8-/16-BIT PARALLEL INTERFACE
Ready/Acknowledge (Active Low)
Interrupt (Active Low)
Serial Data Output
Clock Phase
Interrupt Output (Active Low)
JTAG Data Output
Receive Power-Down (All Ports)
Jitter Attenuator Depth (All Ports)
Jitter Attenuator Select (Tx, Rx, or Disabled) (Port n)
Loopback Control (Port n)
Loopback Select (all ports)
Chip Select (Active Low)
Read Enable (Active Low)/Data Strobe (Active Low)
Write Enable (Active Low)/Read/Write Select
Address Latch Enable
Address Bus (Excluding LSB)
Address Bus LSB/Byte Swap
Data Bus [15:0]
General-Purpose I/O A (Port n)
General-Purpose I/O B (Port n)
Chip Select (Active Low)
Serial Clock
Serial Data Input
Clock Polarity
General-Purpose I/O A (Port n)
General-Purpose I/O B (Port n)
Reference Clock
Clock A—DS3 44.736MHz
Clock B—E3 34.368MHz
Clock C—STS-1 51.84MHz
Clock D—Telecom Bus 77.76MHz or 19.44MHz
CLAD Bypass
JTAG Clock
JTAG Mode Select
JTAG Data Input
JTAG Reset (Active Low)
Digital Core 1.8V Power, 1.8V ±5%
I/O 3.3V Power, 3.3V ±5%
Ground for VDD18 and VDD33
Jitter Attenuator 1.8V Power, 1.8V ±5% (Port n)
Jitter Attenuator Ground (Port n)
Receive 1.8V Power, 1.8V ±5% (Port n)
SPI SERIAL INTERFACE
15 of 130
CLAD
JTAG
FUNCTION
DS32506/DS32508/DS32512
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