93LC56B-I/SN Microchip Technology, 93LC56B-I/SN Datasheet - Page 5

• Manufacturer Part Number: 93LC56B-I/SN
• Description: IC EEPROM 2KBIT 3MHZ 8SOIC
• Manufacturer: Microchip Technology

Specifications of 93LC56B-I/SN

• Memory Size: 2K (128 x 16)
• Package / Case: 8-SOIC (3.9mm Width)
• Operating Temperature: -40°C ~ 85°C
• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Speed: 2MHz, 3MHz
• Interface: Microwire, 3-Wire Serial
• Voltage - Supply: 2.5 V ~ 5.5 V
• Organization: 128 K x 16
• Interface Type: Microwire
• Maximum Clock Frequency: 2 MHz
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.5 V
• Maximum Operating Current: 0.5 mA
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 2.5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 93LC56B-I/SNG

2.0
When the ORG* pin is connected to V
organization is selected. When it is connected to
ground, the (x8) organization is selected. Instructions,
addresses and write data are clocked into the DI pin on
the rising edge of the clock (CLK). The DO pin is
normally held in a HIGH-Z state except when reading
data from the device, or when checking the READY/
BUSY status during a programming operation. The
READY/BUSY status can be verified during an Erase/
Write operation by polling the DO pin; DO low indicates
that programming is still in progress, while DO high
indicates the device is ready. DO will enter the HIGH-Z
state on the falling edge of CS.
2.1
The START bit is detected by the device if CS and DI
are both high with respect to the positive edge of CLK
for the first time.
Before a START condition is detected, CS, CLK, and DI
may change in any combination (except to that of a
START condition), without resulting in any device
operation (READ, WRITE, ERASE, EWEN, EWDS,
ERAL, or WRAL). As soon as CS is high, the device is
no longer in Standby mode.
An instruction following a START condition will only be
executed if the required opcode, address and data bits
for any particular instruction are clocked in.
 2003 Microchip Technology Inc.
FUNCTIONAL DESCRIPTION
START Condition
93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C
CC
, the (x16)
2.2
It is possible to connect the Data In and Data Out pins
together. However, with this configuration it is possible
for a “bus conflict” to occur during the “dummy zero”
that precedes the Read operation, if A0 is a logic high
level. Under such a condition the voltage level seen at
Data Out is undefined and will depend upon the relative
impedances of Data Out and the signal source driving
A0. The higher the current sourcing capability of A0,
the higher the voltage at the Data Out pin. In order to
limit this current, a resistor should be connected
between DI and DO.
2.3
All modes of operation are inhibited when V
a typical voltage of 1.5V for '93AA' and '93LC' devices
or 3.8V for '93C' devices.
The EWEN and EWDS commands give additional
protection against accidentally programming during
normal operation.
After power-up, the device is automatically in the
EWDS mode. Therefore, an EWEN instruction must be
performed before the initial ERASE or WRITE instruction
can be executed.
Block Diagram
ORG*
DI
CLK
Note:
CS
*ORG input is not available on A/B devices
Data In/Data Out (DI/DO)
Data Protection
Data Register
V
For added protection, an EWDS command
should be performed after every write
operation.
CC
Memory
Register
Array
Decode
Clock
Mode
Logic
V
SS
Address
Decoder
Address
Counter
DS21794B-page 5
Output
Buffer
CC
is below
DO