24AA02E48-I/SN Microchip Technology, 24AA02E48-I/SN Datasheet - Page 8

• Manufacturer Part Number: 24AA02E48-I/SN
• Description: IC EEPROM 2KBIT 400KHZ 8SOIC
• Manufacturer: Microchip Technology

Specifications of 24AA02E48-I/SN

• Memory Size: 2K (256 x 8)
• Package / Case: 8-SOIC (3.9mm Width)
• Format - Memory: EEPROMs - Serial (with MAC Address)
• Memory Type: EEPROM
• Speed: 100kHz, 400kHz
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 1.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Organization: 256 K x 8
• Interface Type: I2C
• Maximum Clock Frequency: 0.1 MHz
• Access Time: 3500 ns
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 1.7 V
• Maximum Operating Current: 3 mA
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 1.8 V , 2.5 V , 3.3 V , 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

24AA02E48/24AA025E48
5.0
A control byte is the first byte received following the
Start condition from the master device. The control byte
consists
24AAXXXE48, this is set as ‘
write operations. For the 24AA02E48 the next three
bits of the control byte are “don’t cares”.
For the 24AA025E48, the next three bits of the control
byte are the Chip Select bits (A2, A1, A0). The Chip
Select bits allow the use of up to eight 24AA025E48
devices on the same bus and are used to select which
device is accessed. The Chip Select bits in the control
byte must correspond to the logic levels on the corre-
sponding A2, A1 and A0 pins for the device to respond.
These bits are in effect the three Most Significant bits of
the word address.
For the 6-pin SOT-23 package, the A2 address pin is
not available. During device addressing, the A2 Chip
Select bit should be set to ‘0’.
The last bit of the control byte defines the operation to
be performed. When set to ‘
selected. When set to ‘
Following the Start condition, the 24AAXXXE48 moni-
tors the SDA bus, checking the device type identifier
being transmitted and, upon a
device outputs an Acknowledge signal on the SDA line.
Depending on the state of the R/W bit, the
24AAXXXE48 will select a read or write operation.
FIGURE 5-2:
DS22124D-page 8
Operation
Read
Write
DEVICE ADDRESSING
Note:
of
a
Control
1010
1010
Code
1
four-bit
* Bits A0, A1 and A2 are “don’t cares” for the 24AA02E48.
Control
Code
0
0
ADDRESS SEQUENCE BIT ASSIGNMENTS
’, a write operation is selected.
1
Control Byte
control
1010’
Chip Address
Chip Address
Chip Select
0
1
‘1010’
’, a read operation is
A2* A1* A0*
binary for read and
Select
Chip
code.
bits
code, the slave
R/W
For
R/W
1
0
the
FIGURE 5-1:
5.1
The Chip Select bits A2, A1 and A0 can be used to
expand the contiguous address space for up to 16K bits
by adding up to eight 24AA025E48 devices on the
same bus. In this case, software can use A0 of the con-
trol byte as address bit A8, A1 as address bit A9 and
A2 as address bit A10. It is not possible to sequentially
read across device boundaries.
For the SOT-23 package, up to four 24AA025E48
devices can be added for up to 8K bits of address
space. In this case, software can us A0 of the control
byte as address bit A8, and A1 as address bit A9. It is
not possible to sequentially read across device
boundaries.
A
7
Start Bit
Note:
•
S
Address Low Byte
•
Contiguous Addressing Across
Multiple Devices
1
Control Code
* Bits A0, A1 and A2 are “don’t cares” for
the 24AA02E48.
•
0
•
Slave Address
1
•
CONTROL BYTE
ALLOCATION
 2010 Microchip Technology Inc.
0
•
A2* A1* A0* R/W ACK
A
0
Select
Chip
Bits
Acknowledge Bit
Read/Write Bit