72V285L10PF IDT, 72V285L10PF Datasheet - Page 8
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72V285L10PF
Manufacturer Part Number
72V285L10PF
Description
FIFO
Manufacturer
IDT
Datasheet
1.72V285L10PFG.pdf
(25 pages)
Specifications of 72V285L10PF
Part # Aliases
IDT72V285L10PF
rizes the control pins and sequence for both serial and parallel programming
modes. For a more detailed description, see discussion that follows.
NOTES:
1. n = Empty Offset, Default Values: n = 127 when parallel offset loading is selected or n = 1,023 when serial offset loading is selected.
2. m = Full Offset, Default Values: m = 127 when parallel offset loading is selected or m = 1,023 when serial offset loading is selected.
NOTES:
1. n = Empty Offset, Default Values: n = 127 when parallel offset loading is selected or n = 1,023 when serial offset loading is selected.
2. m = Full Offset, Default Values: m = 127 when parallel offset loading is selected or m = 1,023 when serial offset loading is selected.
IDT72V275/72V285 3.3V CMOS SUPERSYNC FIFO
32,768 x 18 and 65,536 x 18
Figure 4, Programmable Flag Offset Programming Sequence, summa-
TABLE 2. STATUS FLAGS FOR FWFT MODE
TABLE 1. STATUS FLAGS FOR IDT STANDARD MODE
Number of
Words in
FIFO
Number of
Words in
FIFO
16,386 to (32,769-(m+1))
16,385 to (32,768-(m+1))
(32,768-m)
(32,769-m)
(n+1) to 16,384
(n+2) to 16,385
72V275
1 to n
72V275
32,768
1 to n+1
32,769
0
(2)
0
to 32,768
to 32,767
(1)
TM
(1)
(2)
32,770 to (65,537-(m+1))
32,769 to (65,536-(m+1))
8
(65,536-m)
(65,537-m)
Master Reset, regardless of whether serial or parallel programming has been
selected.
(n+2) to 32,769
(n+1) to 32,768
The offset registers may be programmed (and reprogrammed) any time after
72V285
1 to n+1
72V285
65,537
1 to n
65,536
0
0
(2)
to 65,536
to 65,535
(1)
(1)
(2)
FF
IR
H
H
H
H
H
L
L
L
L
L
H
L
COMMERCIAL AND INDUSTRIAL
PAF HF
PAF HF
H
H
H
H
H
H
H
H
L
L
L
L
TEMPERATURE RANGES
H
H
H
L
L
L
H
H
H
L
L
L
PAE EF
PAE OR
H
H
H
H
L
L
H
H
H
H
L
L
4512 drw 05
H
H
H
H
H
H
L
L
L
L
L
L