MAX9665ETP+ Maxim Integrated, MAX9665ETP+ Datasheet - Page 16

• Manufacturer Part Number: MAX9665ETP+
• Description: LCD Gamma Buffers 6/8/10-Channel 10-Bit Nonvolatile Programmable Gamma and VCOM Reference Voltages
• Manufacturer: Maxim Integrated

6/8/10-Channel, 10-Bit, Nonvolatile Programmable
Gamma and VCOM Reference Voltages
A write to the MAX9665/MAX9666/MAX9667 consists of
transmitting a START condition, the slave address with
the R/W bit set to 0, one data byte of data to configure
the internal register address pointer, one or more data
bytes, and a STOP condition. Figure 7 illustrates the
frame format for writing one byte of data to the
MAX9665/MAX9666/MAX9667.
The slave address with the R/W bit set to 0 indicates
that the master intends to write data to the MAX9665/
MAX9666/MAX9667. The MAX9665/MAX9666/MAX9667
acknowledge receipt of the address byte during the mas-
ter-generated ninth SCL pulse.
The second byte transmitted from the master config-
ures the MAX9665/MAX9666/MAX9667’s internal reg-
ister address pointer. The pointer tells the MAX9665/
MAX9666/MAX9667 where to write the next byte of
data. An acknowledge pulse is sent by the MAX9665/
MAX9666/MAX9667 upon receipt of the address
pointer data.
The third byte sent to the MAX9665/MAX9666/MAX9667
contains the data that is written to the chosen register.
An acknowledge pulse from the MAX9665/MAX9666/
MAX9667 signals receipt of the data byte. The address
pointer autoincrements to the next register address
after each received data byte. This autoincrement fea-
ture allows a master to write to sequential register
address locations within one continuous frame. The
master signals the end of transmission by issuing a
STOP condition.
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Write Data Format
The master presets the address pointer by first sending
the MAX9665/MAX9666/MAX9667’s slave address with
the R/W bit set to 0 followed by the register address
after a START condition. The MAX9665/MAX9666/
MAX9667 acknowledge receipt of the slave address
and the register address by pulling SDA low during the
ninth SCL clock pulse. A REPEATED START condition
is then sent followed by the slave address with the R/W
bit set to 1. The MAX9665/MAX9666/MAX9667 transmit
the contents of the specified register. Transmitted data
is valid on the rising edge of the master-generated seri-
al clock (SCL). The address pointer autoincrements
after each read data byte. This autoincrement feature
allows all registers to be read sequentially within one
continuous frame. A STOP condition can be issued
after any number of read data bytes. If a STOP condi-
tion is issued followed by another read operation, the
first data byte to be read is from the register address
location set by the previous transaction and not 0x00
and subsequent reads autoincrement the address
pointer until the next STOP condition. Attempting to
read from register addresses higher than the highest
valid address locations (0x13 for MAX9665, 0x17 for
MAX9666, 0x1B for MAX9667) in repeated reads from a
dummy register containing all one data. The master
acknowledges receipt of each read byte during the
acknowledge clock pulse. The master must acknowl-
edge all correctly received bytes except the last byte.
The final byte must be followed by a not acknowledge
from the master and then a STOP condition. Figures 8
and 9 illustrate the frame format for reading data from
the MAX9665/MAX9666/MAX9667.
Read Data Format