MAX9665ETP+ Maxim Integrated, MAX9665ETP+ Datasheet - Page 14

• Manufacturer Part Number: MAX9665ETP+
• Description: LCD Gamma Buffers 6/8/10-Channel 10-Bit Nonvolatile Programmable Gamma and VCOM Reference Voltages
• Manufacturer: Maxim Integrated

6/8/10-Channel, 10-Bit, Nonvolatile Programmable
Gamma and VCOM Reference Voltages
For VCOM MTP programming through the single-wire
interface, see the Single-Wire Interface section.
Two registers, VCOMMIN and VCOMMAX, are provided
to set the minimum and maximum VCOM register value.
These two registers are accessed through the I
face and can be written to and read from MTP memory.
If any adjustment, either through I
interface takes the VCOM register value less than
VCOMMIN, then the value in VCOMMIN is stored in the
VCOM register. Similarly, if any adjustment, either
through I
register value greater than VCOMMAX, then the value
in VCOMMAX is stored in the VCOM register.
The MAX9665/MAX9666/MAX9667 feature an I
SMBus™-compatible, 2-wire serial interface consisting
of a serial-data line (SDA) and a serial-clock line (SCL).
SDA and SCL facilitate communication between the
devices and the master at clock rates up to 400kHz.
Figure 4 shows the 2-wire interface timing diagram. The
master generates SCL and initiates data transfer on the
bus. A master device writes data to the devices by
transmitting the proper slave address followed by the
register address and then the data word. Each transmit
sequence is framed by a START (S) or REPEATED
START (Sr) condition and a STOP (P) condition. Each
word transmitted to the MAX9665/MAX9666/MAX9667 is
8 bits long and followed by an acknowledge clock
pulse. A master reading data from the devices transmits
the proper slave address followed by a series of nine
SCL pulses. The devices transmit data on SDA in sync
with the master-generated SCL pulses. The master
Figure 4. I
SMBus is a trademark of Intel Corp.
14
SDA
SCL
______________________________________________________________________________________
t
HD,STA
2
2
C Serial-Interface Timing Diagram
C or the single-wire interface takes the VCOM
CONDITION
START
Through the Single-Wire Interface
t
LOW
VCOM Programming Range
t
R
t
t
SU,DAT
HIGH
2
C or the single-wire
t
F
I
2
C Interface
t
HD,DAT
2
C inter-
2
C/
t
SU,STA
START CONDITION
acknowledges receipt of each byte of data. Each read
sequence is framed by a START or REPEATED START
condition, a not acknowledge, and a STOP condition.
SDA operates as both an input and an open-drain out-
put. A pullup resistor, typically greater than 500Ω, is
required on the SDA bus. SCL operates as only an
input. A pullup resistor, typically greater than 500Ω, is
required on SCL if there are multiple masters on the bus,
or if the master in a single-master system has an open-
drain SCL output. Series resistors in line with SDA and
SCL are optional. Series resistors protect the digital
inputs of the devices from high-voltage spikes on the
bus lines, and minimize crosstalk and undershoot of the
bus signals.
One data bit is transferred during each SCL cycle. The
data on SDA must remain stable during the high period
of the SCL pulse. Changes in SDA while SCL is high
are control signals (see the START and STOP
Conditions section). SDA and SCL idle high when the
I
SDA and SCL idle high when the bus is not in use. A
master initiates communication by issuing a START
condition. A START condition is a high-to-low transition
on SDA with SCL high. A STOP condition is a low-to-
high transition on SDA while SCL is high (Figure 5). A
START condition from the master signals the beginning
of a transmission to the MAX9665/MAX9666/MAX9667.
The master terminates transmission, and frees the bus,
by issuing a STOP condition. The bus remains active if
a REPEATED START condition is generated instead of
a STOP condition.
2
REPEATED
C bus is not busy.
t
HD,STA
t
START and STOP Conditions
SP
t
SU,STO
CONDITION
STOP
t
Bit Transfer
BUF
CONDITION
START