24LC02BT-I/OT Microchip Technology, 24LC02BT-I/OT Datasheet - Page 10

• Manufacturer Part Number: 24LC02BT-I/OT
• Description: IC EEPROM 2KBIT 400KHZ SOT23-5
• Manufacturer: Microchip Technology

Specifications of 24LC02BT-I/OT

• Memory Size: 2K (256 x 8)
• Package / Case: SOT-23-5, SC-74A, SOT-25
• Operating Temperature: -40°C ~ 85°C
• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Speed: 400kHz
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.5 V ~ 5.5 V
• Organization: 256 K x 8
• Interface Type: I2C
• Maximum Clock Frequency: 0.4 MHz
• Access Time: 900 ns
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.5 V
• Maximum Operating Current: 3 mA
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 2.5 V, 5.5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 24LC02BT-I/OT; 24LC02BTI/OT

24AA02/24LC02B
8.0
Read operations are initiated in the same way as write
operations, with the exception that the R/W bit of the
slave address is set to ‘
of read operations: current address read, random read
and sequential read.
8.1
The 24XX02 contains an address counter that main-
tains the address of the last word accessed, internally
incremented by ‘
(either a read or write operation) was to address
next current address read operation would access data
from address
with R/W bit set to ‘
edge and transmits the 8-bit data word. The master will
not acknowledge the transfer, but does generate a Stop
condition, and the 24XX02 discontinues transmission
(Figure 8-1).
8.2
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, the word address must first
be set. This is accomplished by sending the word
address to the 24XX02 as part of a write operation.
Once the word address is sent, the master generates a
Start condition following the acknowledge. This
terminates the write operation, but not before the inter-
nal Address Pointer is set. The master then issues the
control byte again, but with the R/W bit set to a ‘
24XX02 will then issue an acknowledge and transmit
the 8-bit data word. The master will not acknowledge
the transfer, but does generate a Stop condition, and
the 24XX02 will discontinue transmission (Figure 8-2).
FIGURE 8-1:
DS21709J-page 10
READ OPERATION
Current Address Read
Random Read
n + 1
Bus Activity
Master
SDA Line
Bus Activity
x = “don’t care”
1
’. Therefore, if the previous access
1
. Upon receipt of the slave address
’, the 24XX02 issues an acknowl-
CURRENT ADDRESS READ
1
’. There are three basic types
S
T
A
R
T
S
1
0
1
1 0
n
’. The
Control
, the
Byte
x x x
Select
Block
Bits
8.3
Sequential reads are initiated in the same way as a
random read, except that once the 24XX02 transmits
the first data byte, the master issues an acknowledge
as opposed to a Stop condition in a random read. This
directs the 24XX02 to transmit the next sequentially-
addressed 8-bit word (Figure 8-3).
To provide sequential reads, the 24XX02 contains an
internal Address Pointer that is incremented by one
upon completion of each operation. This Address
Pointer allows the entire memory contents to be serially
read during one operation.
8.4
The 24XX02 employs a V
which disables the internal erase/write logic if the V
is below 1.5V at nominal conditions.
The SCL and SDA inputs have Schmitt Trigger and
filter circuits which suppress noise spikes to assure
proper device operation, even on a noisy bus.
1
A
C
K
Sequential Read
Noise Protection
Data (n)
© 2009 Microchip Technology Inc.
CC
threshold detector circuit
N
o
C
A
K
P
S
T
O
P
CC