GLS85LS1008B-M-I-1S-ED100 Greenliant, GLS85LS1008B-M-I-1S-ED100 Datasheet - Page 5

• Manufacturer Part Number: GLS85LS1008B-M-I-1S-ED100
• Description: Solid State Drives - SSD 8GByte PATA NAN SSD 14x24mm BGA, I-temp
• Manufacturer: Greenliant

Specifications of GLS85LS1008B-M-I-1S-ED100

• Rohs: yes

Table 3-1: Pin Assignments (2 of 2)
These specifications are subject to change without notice.
© 2012 Greenliant Systems
Serial Communication Interface (SCI)
Miscellaneous
GLS85LP1004B / 1008B / 1016B / 1032A
Commercial Grade PATA NANDrive™
SCIDOUT
WP#/PD#
IOCS16#
RESET#
Symbol
PDIAG#
SCICLK
SCIDIN
IORDY
DASP#
INTRQ
DNU
V
V
SS
DD
G4, G6, G7, K4,
E2, E9, K5, L5,
G5, J7, L4, L6,
B10, D2, D3,
A10, B1, B9,
M5, M6, M7,
R10, T1, T2,
M8, N2, N3,
D4, D5, D6,
L7, M3, M4,
N4, N5, N6,
N7, N8, N9,
R1, R2, R9,
A1, A2, A9,
E5, E6, F5,
K6, K7, J9
T9, T10
Pin No.
M2, M9
91-Ball
K9
D9
E4
D8
D7
E7
F6
J4
J8
J2
Type
PWR
PWR
Pin
I/O
I/O
O
O
O
O
I
I
I
I
I/O Type
I1U/O2
I1U/O4
I2U
I1U
I1D
I2U
O2
O3
O2
O2
Do not use. All these pins should not be connected.
IORDY: When in PIO mode, the device is not ready to respond to a
data transfer request. This signal is negated to extend the Host
transfer cycle from the assertion of IORD# or IOWR#. However, it is
never negated by this controller. (This pin supports three functions)
DDMARDY#: When Ultra DMA mode DMA Write is active, this signal
is asserted by the device to indicate that the device is ready to receive
Ultra DMA data-out bursts. The device may negate DDMARDY# to
pause an Ultra DMA transfer.
DSTROBE: When Ultra DMA mode DMA Read is active, this signal is
the data-in strobe generated by the device. Both the rising and falling
edges of DSTROBE cause data to be latched by the Host. The device
may stop generating DSTROBE edges to pause an Ultra DMA data-in
burst.
This output signal is asserted low when the device is indicating a
Word data transfer cycle.
This signal is the active high Interrupt Request to the Host.
The Pass Diagnostic signal in the Master/Slave handshake protocol.
The Drive Active/Slave Present signal in the Master/Slave handshake
protocol.
This input pin is the active low hardware reset from the Host.
SCI data output. No external pull-up or pull-down resistor should
connect to this signal.
SCI data input
SCI clock
The WP#/PD# pin can be used for either the Write Protect mode or
Power-down mode, but only one mode is active at any time. The Write
Protect or Power-down modes can be selected through the host
command. The Write Protect mode is the factory default setting.
Ground
VDD (3.3V)
5
Name and Functions
Fact Sheet 02.000
June 2012
06/01/2012
S71438-F