GLS85LS1008B-M-I-1S-ED100 Greenliant, GLS85LS1008B-M-I-1S-ED100 Datasheet - Page 2

• Manufacturer Part Number: GLS85LS1008B-M-I-1S-ED100
• Description: Solid State Drives - SSD 8GByte PATA NAN SSD 14x24mm BGA, I-temp
• Manufacturer: Greenliant

Specifications of GLS85LS1008B-M-I-1S-ED100

• Rohs: yes

1.0 GENERAL DESCRIPTION
Each PATA NANDrive contains an integrated PATA NAND flash memory controller and NAND flash die in a BGA or LBGA
package. Refer to Figure 2-1 for the Commercial Grade PATA NANDrive block diagram.
1.1 Optimized PATA NANDrive
The heart of the PATA NANDrive is the PATA NAND
flash memory controller, which translates standard
PATA signals into flash media data and control
signals. The following components contribute to the
PATA NANDrive’s operation.
1.1.1 Microcontroller Unit (MCU)
The MCU transfers the ATA/IDE commands into data
and control signals required for flash media operation.
1.1.2 Internal Direct Memory Access (DMA)
The PATA NANDrive uses internal DMA allowing
instant data transfer from/to buffer to/from flash media.
This
overhead associated with the traditional, firmware-
based approach, thereby increasing the data transfer
rate.
1.1.3 Power Management Unit (PMU)
The PMU controls the power consumption of the
PATA NANDrive. The PMU dramatically reduces the
power consumption of the PATA NANDrive by putting
the part of the circuitry that is not in operation into
sleep mode.
The Flash File System handles inadvertent power
interrupts and has auto-recovery capability to ensure
the PATA NANDrive’s data integrity. For regular
power
IDLE_IMMEDIATE command and wait for command
ready before powering down the PATA NANDrive.
1.1.4 Embedded Flash File System
The embedded flash file system is an integral part of
the PATA NANDrive. It contains MCU firmware that
performs the following tasks:
These specifications are subject to change without notice.
© 2012 Greenliant Systems
GLS85LP1004B / 1008B / 1016B / 1032A
Commercial Grade PATA NANDrive™
1. Translates host side signals into flash media
2. Provides flash media wear leveling to spread
3. Keeps track of data file structures
4. Manages system security for the selected
5. Stores the data in flash media upon completion
writes and reads
the flash writes across all memory address
space to increase the longevity of flash media
protection zones
of a Write command (The PATA NANDrive does
not perform Post-Write operations, except for
when the write cache is enabled)
implementation
management,
the
eliminates
Host
must
microcontroller
send
an
2
1.1.5 Error Correction Code (ECC)
High performance is achieved through optimized
hardware error detection and correction.
1.1.6 Serial Communication Interface (SCI)
The Serial Communication Interface (SCI) is designed
for manufacturing error reporting. During the design
process, always provide access to the SCI port in the
PCB design to aid in design validation.
1.1.7 Multi-tasking Interface
The multi-tasking interface enables fast, sustained
write performance by allowing concurrent Read,
Program and Erase operations to multiple flash media.
1.2 SMT Reflow Consideration
The PATA NANDrive family utilizes standard NAND
flash for data storage. Because the high temperature
in a surface-mount soldering reflow process can alter
the content on NAND flash, do not program the PATA
NANDrive before the reflow process.
1.3 Advanced NAND Management
The PATA NANDrive’s integrated controller uses
advanced wear-leveling algorithms to substantially
increase the longevity of NAND flash media. Wear
caused by data writes is evenly distributed in all or
select blocks in the device that prevents “hot spots” in
locations that are programmed and erased extensively.
This effective wear-leveling technique results in
optimized device endurance, enhanced data retention
and higher reliability required by long-life applications.
Fact Sheet 02.000
June 2012
06/01/2012
S71438-F