FM24C256B-G Cypress Semiconductor, FM24C256B-G Datasheet
FM24C256B-G
Specifications of FM24C256B-G
Related parts for FM24C256B-G
FM24C256B-G Summary of contents
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... Supports Legacy Timing for 100 kHz & 400 kHz Description The FM24C256 is a 256-kilobit nonvolatile memory employing an advanced ferroelectric process. A ferroelectric random access memory or FRAM is nonvolatile and performs reads and writes like a RAM. It provides reliable data retention for 45 years while eliminating the complexities, overhead, and ...
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Counter SDA Serial to Parallel SCL WP Control Logic A0-A2 Pin Description Pin Name Type Pin Description A0-A2 Input Address 2-0: These pins are used to select one devices of the same type on the same ...
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... The upper address bit should be set to 0 for compatibility with higher density devices in the future. The memory is read or written at the speed of the two-wire bus. Unlike an EEPROM not necessary to poll the device for a ready condition since writes occur at bus speed. By the time a new bus transaction can be shifted into the part, a write operation is complete ...
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... All operations using the FM24C256 must end with a Stop condition operation is pending when a Stop is asserted, the operation will be aborted. The master must have control of SDA (not a memory read) in order to assert a Stop condition. Start Condition A Start condition is indicated when the bus master drives SDA from high to low while the SCL signal is high ...
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... FRAM. Since the read and write access times of the underlying memory are the same, the user experiences no delay on the bus. The entire memory cycle occurs in less time than a single bus clock. Therefore, any operation including a read or write ...
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Start By Master S Slave Address 0 By FM24C256 Start By Master X S Slave Address FM24C256 Read Operation There are two types of read operations. They are current address read and selective address read ...
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Start By Master By FM24C256 Start Address By Master S Slave Address By FM24C256 Start Address By Master S Slave Address 0 A Address MSB By FM24C256 Endurance A FRAM internally operates with a read and restore mechanism. Therefore, endurance ...
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Electrical Specifications Absolute Maximum Ratings Symbol V Voltage Voltage on any signal pin with respect Storage Temperature STG T Lead temperature (Soldering, 10 seconds) LEAD V Electrostatic Discharge Voltage ESD - Human ...
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AC Parameters (T = -40° 85° Symbol Parameter f SCL Clock Frequency SCL t Clock Low Period LOW t Clock High Period HIGH t SCL Low to SDA Data Out Valid AA t Bus ...
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Diagram Notes All start and stop timing parameters apply to both read and write cycles. Clock specifications are identical for read and write cycles. Write timing parameters apply to slave address, word address, and write data bits. Functional relationships are ...
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Mechanical Drawing 8-pin EIAJ SOIC Pin 1 5.23 0.10 ± 1.27 0.36 0.50 All dimensions in millimeters. EIAJ SOIC Package Marking Scheme Legend: XXXXXX= part number LLLLLLL= lot code RIC=Ramtron Int’l Corp, YY=year, WW=work week XXXXXXX-G LLLLLLL FM24C256, “Green” EIAJ ...
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... OL Updated package drawing and dimensions. Rewrote description of the internal memory architecture and endurance section. Added “part marking” note to Ordering Information (pg 1). Added “green” packaging option. Added ESD and package MSL ratings. Changed storage temperature. New rev. number and 1 with updated scheme ...