74LVC1G08GW-Q100,1 NXP Semiconductors, 74LVC1G08GW-Q100,1 Datasheet - Page 2

no-image

74LVC1G08GW-Q100,1

Manufacturer Part Number
74LVC1G08GW-Q100,1
Description
Logic Gates
Manufacturer
NXP Semiconductors
Datasheet

Specifications of 74LVC1G08GW-Q100,1

Rohs
yes
Product
AND
Logic Family
74LVC
Number Of Gates
1
Number Of Lines (input / Output)
2 /
Propagation Delay Time
10.5 ns
Supply Voltage - Max
5.5 V
Supply Voltage - Min
1.65 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Package / Case
TSSOP-5
Maximum Power Dissipation
250 mW
Minimum Operating Temperature
- 40 C
Number Of Input Lines
2
Operating Temperature Range
- 40 C to + 125 C
Output Current
50 mA
Power Dissipation
250 mW
NXP Semiconductors
3. Ordering information
Table 1.
4. Marking
Table 2.
[1]
5. Functional diagram
6. Pinning information
74LVC1G08_Q100
Product data sheet
Type number
74LVC1G08GW-Q100 40 C to +125 C
74LVC1G08GV-Q100
Type number
74LVC1G08GW-Q100
74LVC1G08GV-Q100
Fig 1.
Fig 4.
The pin 1 indicator is located on the lower left corner of the device, below the marking code.
1
2
Logic symbol
Pin configuration SOT353-1 and SOT753
Ordering information
Marking
B
A
6.1 Pinning
mna113
Package
Temperature
range
40 C to +125 C
Y
4
All information provided in this document is subject to legal disclaimers.
Fig 2.
Name
TSSOP5
SC-74A
GND
B
A
1
2
IEC logic symbol
Rev. 1 — 9 July 2012
74LVC1G08-Q100
1
2
3
plastic thin shrink small outline package; 5 leads;
Description
body width 1.25 mm
plastic surface-mounted package; 5 leads
aaa-003146
&
Marking code
VE
V08
mna114
5
4
4
V
Y
CC
[1]
74LVC1G08-Q100
Fig 3.
A
B
Logic diagram
Single 2-input AND gate
© NXP B.V. 2012. All rights reserved.
Version
SOT353-1
SOT753
mna221
2 of 13
Y

Related parts for 74LVC1G08GW-Q100,1