74HC132D-Q100 NXP Semiconductors, 74HC132D-Q100 Datasheet

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74HC132D-Q100

Manufacturer Part Number
74HC132D-Q100
Description
Logic Gates 2-IN NAND Gate 6V
Manufacturer
NXP Semiconductors
Datasheet

Specifications of 74HC132D-Q100

Product
NAND
Logic Family
74HC
Number Of Gates
4
Number Of Lines (input / Output)
2 /
Propagation Delay Time
190 ns
Supply Voltage - Max
6 V
Supply Voltage - Min
2 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Package / Case
SO-14
Maximum Power Dissipation
500 mW
Minimum Operating Temperature
- 40 C
Number Of Input Lines
2
Operating Temperature Range
- 40 C to + 125 C
Output Current
25 mA
Power Dissipation
500 mW
Part # Aliases
74HC132D-Q100,118
1. General description
2. Features and benefits
3. Applications
The 74HC132-Q100; 74HCT132-Q100 is a high-speed Si-gate CMOS device and is pin
compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with
JEDEC standard No. 7A
The 74HC132-Q100; 74HCT132-Q100 is a quad 2-input NAND gate with Schmitt-trigger
inputs. This device features reduced input threshold levels to allow interfacing to TTL logic
levels. Inputs also include clamp diodes, this enables the use of current limiting resistors
to interface inputs to voltages in excess of V
changing input signals into sharply defined jitter-free output signals.
The inputs switch at different points for positive and negative-going signals. The difference
between the positive voltage V
hysteresis voltage V
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
74HC132-Q100; 74HCT132-Q100
Quad 2-input NAND Schmitt trigger
Rev. 2 — 13 August 2012
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
ESD protection:
Multiple package options
Wave and pulse shapers
Astable multivibrators
Monostable multivibrators
Specified from 40 C to +85 C and from 40 C to +125 C
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
H
.
T+
and the negative voltage V
CC
. Schmitt trigger inputs transform slowly
T
is defined as the input
Product data sheet

Related parts for 74HC132D-Q100

74HC132D-Q100 Summary of contents

Page 1

Quad 2-input NAND Schmitt trigger Rev. 2 — 13 August 2012 1. General description The 74HC132-Q100; 74HCT132-Q100 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL specified in compliance with ...

Page 2

... NXP Semiconductors 4. Ordering information Table 1. Ordering information Type number Package Temperature range Name 40 C to +125 C 74HC132D-Q100 74HCT132D-Q100 40 C to +125 C 74HC132PW-Q100 74HCT132PW-Q100 5. Functional diagram mna407 Fig 1. ...

Page 3

... NXP Semiconductors 6. Pinning information 6.1 Pinning Fig 4. Pin configuration SO14 and TSSOP14 6.2 Pin description Table 2. Pin description Symbol Pin 10 GND Functional description [1] Table 3. Function table Input [ HIGH voltage level LOW voltage level don’t care. ...

Page 4

... NXP Semiconductors 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter V supply voltage CC I input clamping current IK I output clamping current OK I output current O I supply current CC I ground current ...

Page 5

... NXP Semiconductors 10. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 74HC132-Q100 V HIGH-level output voltage = 20  20  20  4.0 mA 5.2 mA LOW-level ...

Page 6

... NXP Semiconductors 11. Dynamic characteristics Table 7. Dynamic characteristics GND = pF; for load circuit see L Symbol Parameter Conditions 74HC132-Q100 t propagation delay nA nY; see transition time see power dissipation per package capacitance 74HCT132-Q100 t propagation delay nA nY; see ...

Page 7

... NXP Semiconductors 12. Waveforms Measurement points are given in V and V are typical voltage output levels that occur with the output load Fig 5. Input to output propagation delays Table 8. Measurement points Type Input V M 74HC132-Q100 0.5V CC 74HCT132-Q100 1.3 V Test data is given in Table Definitions test circuit: ...

Page 8

... NXP Semiconductors Table 9. Test data Type Input V I 74HC132-Q100 V CC 74HCT132-Q100 3.0 V 13. Transfer characteristics Table 10. Transfer characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V); see Symbol Parameter Conditions 74HC132-Q100 V positive-going threshold voltage negative-going V = 2.0 V T ...

Page 9

... NXP Semiconductors  , && — Fig 9. Typical 74HC132-Q100 transfer characteristics 74HC_HCT132_Q100 Product data sheet 74HC132-Q100; 74HCT132-Q100 DDD , && —  , && P$          All information provided in this document is subject to legal disclaimers. Rev. 2 — 13 August 2012 Quad 2-input NAND Schmitt trigger ...

Page 10

... NXP Semiconductors  , && P$         4 Fig 10. Typical 74HCT132-Q100 transfer characteristics 15. Application information The slow input rise and fall times cause additional power dissipation, this can be calculated using the following formula add P = additional power dissipation (W); add f = input frequency (MHz); ...

Page 11

... NXP Semiconductors (1) Positive-going edge. (2) Negative-going edge. Fig 11. Average additional supply current as a function of V 0. (1) Positive-going edge. (2) Negative-going edge. Fig 12. Average additional supply current as a function of V 0. 74HC_HCT132_Q100 Product data sheet 74HC132-Q100; 74HCT132-Q100  DYHUDJH , && —$   ...

Page 12

... NXP Semiconductors For 74HC132-Q100 and 74HCT132-Q100: For K-factor see Figure 14 Fig 13. Relaxation oscillator  .        K-factor for 74HC132-Q100 Fig 14. Typical K-factor for relaxation oscillator 74HC_HCT132_Q100 Product data sheet 74HC132-Q100; 74HCT132-Q100 001aac440 1 1  ----------------- - f =  DDD  .   ...

Page 13

... NXP Semiconductors 16. Package outline SO14: plastic small outline package; 14 leads; body width 3 pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.25 1.45 mm 1.75 0.25 0.10 1.25 0.010 0.057 inches 0.069 0.01 0.004 0.049 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...

Page 14

... NXP Semiconductors TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...

Page 15

... NXP Semiconductors 17. Abbreviations Table 11. Abbreviations Acronym Description CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model LSTTL Low-power Schottky Transistor-Transistor Logic MM Machine Model MIL Military 18. Revision history Table 12. Revision history Document ID Release date 74HC_HCT132_Q100 v.2 20120813 • ...

Page 16

... Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...

Page 17

... NXP Semiconductors No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations ...

Page 18

... NXP Semiconductors 21. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 Functional description . . . . . . . . . . . . . . . . . . . 3 8 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 6 12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 13 Transfer characteristics ...

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