74LVC16373ADGG,512 NXP Semiconductors, 74LVC16373ADGG,512 Datasheet
74LVC16373ADGG,512
Specifications of 74LVC16373ADGG,512
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74LVC16373ADGG,512 Summary of contents
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D-type transparent latch with 5 V tolerant inputs/outputs; 3-state Rev. 7 — 18 January 2013 1. General description The 74LVCH16373A and 74LVCH16373A are 16-bit D-type transparent latches featuring separate D-type inputs with bus hold (74LVCH16373A only) for ...
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... NXP Semiconductors 3. Ordering information Table 1. Ordering information Type number Package Temperature range 40 C to +125 C 74LVC16373ADGG 74LVCH16373ADGG 40 C to +125 C 74LVC16373ADL 74LVCH16373ADL 4. Functional diagram 1 1OE 2OE 47 1D0 46 1D1 44 1D2 43 1D3 41 1D4 40 1D5 38 1D6 1D7 37 2D0 36 35 2D1 33 2D2 32 2D3 ...
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... NXP Semiconductors 1D0 1LE 1OE Fig 3. Logic diagram Fig 4. Bus hold circuit 74LVC_LVCH16373A Product data sheet 74LVC16373A; 74LVCH16373A 16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state 1Q0 2D0 D Q LATCH 2LE 2OE to 7 other channels V CC data input to internal circuit mgu771 All information provided in this document is subject to legal disclaimers ...
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... NXP Semiconductors 5. Pinning information 5.1 Pinning Fig 5. Pin configuration SSOP48 and TSSOP48 5.2 Pin description Table 2. Pin description Symbol Pin 1OE 1 2OE 24 1LE 48 2LE 25 GND 4, 10, 15, 21, 28, 34, 39 18, 31 1Q[0: 11, 12 2Q[0:7] 13, 14, 16, 17, 19, 20, 22, 23 1D[0:7] 47, 46, 44, 43, 41, 40, 38, 37 ...
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... NXP Semiconductors 6. Functional description Table 3. Function table [1] Per section of eight bits . Operating modes Enable and read register (transparent mode) Latch and read register Latch register and disable outputs [ HIGH voltage level h = HIGH voltage level one set-up time prior to the HIGH to LOW LE transition ...
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... NXP Semiconductors 8. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter V supply voltage CC V input voltage I V output voltage O T ambient temperature amb t/V input transition rise and fall rate 9. Static characteristics Table 6. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). ...
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... NXP Semiconductors Table 6. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions I OFF-state output GND O current I power-off OFF CC leakage current I supply current I additional per input pin; ...
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... NXP Semiconductors 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Symbol Parameter Conditions t propagation Dn to Qn; see pd delay Qn; see enable time OE to Qn; see ...
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... NXP Semiconductors Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Symbol Parameter Conditions t hold time Dn to LE; see output skew 3.6 V sk(o) CC time C power per input dissipation V CC capacitance ...
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... NXP Semiconductors OE input Qn output LOW-to-OFF OFF-to-LOW Qn output HIGH-to-OFF OFF-to-HIGH Measurement points are given in V and V are typical output voltage levels that occur with the output load Fig 8. 3-state enable and disable times Dn input LE input Measurement points are given in ...
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... NXP Semiconductors Table 8. Measurement points Supply voltage Input 2.7 V 2 3.6 V 2.7 V Test data is given in Table Definitions for test circuit Load resistance Load capacitance including jig and probe capacitance Termination resistance should be equal to output impedance Z ...
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... NXP Semiconductors 12. Package outline TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6 pin 1 index 1 DIMENSIONS (mm are the original dimensions). A UNIT max. 0.15 1.05 mm 1.2 0.25 0.05 0.85 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors SSOP48: plastic shrink small outline package; 48 leads; body width 7 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.4 2.35 mm 2.8 0.25 0.2 2.20 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION IEC SOT370-1 Fig 12 ...
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... Release Data sheet status date 20130118 Product data sheet • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • Table 5, Table ...
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... Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... D-type transparent latch with 5 V tolerant inputs/outputs; 3-state NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ ...
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... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 Functional description . . . . . . . . . . . . . . . . . . . 5 7 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12 13 Abbreviations ...