MAX3822UCM+ Maxim Integrated, MAX3822UCM+ Datasheet - Page 8

• Manufacturer Part Number: MAX3822UCM+
• Description: Limiting Amplifiers Integrated Circuits (ICs)
• Manufacturer: Maxim Integrated

Specifications of MAX3822UCM+

• Rohs: yes
• Factory Pack Quantity: 250

stage of the MAX3822, including package capacitance
and bond-wire inductance. The additional 0.4pF
capacitance on the output represents the ESD diode’s
junction capacitance and a small contribution by the
bond pad. For more information about the CML electri-
cal specifications and interfacing to other protocols,
refer to Application Note HFAN-1.0, Introduction to
LVDS, PECL, and CML.
Each limiting amplifier on the MAX3822 provides
approximately 50dB of gain. An input offset as small as
1mV reduces the power-detection circuitry’s accuracy
+3.3V, 2.5Gbps Quad Limiting Amplifier
Figure 2. Input Structure
8
Figure 3. Output Structure
_______________________________________________________________________________________
50Ω
GND
50Ω
ESD
DIODES
IN+
IN-
DIE
V
CC
PACKAGE
0.2pF
0.2pF
0.4pF
0.4pF
Offset Correction
1.5nH
1.5nH
1.5nH
1.5nH
0.4pF
0.4pF
PACKAGE
DIE
0.2pF
0.2pF
GND
OUT+
OUT-
V
CC
ESD
DIODES
50Ω
and may cause deterministic jitter through an increase
of PWD.
Each of the MAX3822’s integrated limiting amplifiers
includes a DC cancellation loop that provides offset
correction to the CML output signal in addition to low-
frequency power-supply noise rejection. The DC can-
cellation loop consists of a low-pass filter and a
high-gain amplifier. The input voltage difference of the
CML output buffer is amplified, sent through a low-pass
filter, inverted, and summed up with the input signal
that drives the high-gain input stage. This removes from
the output signal all frequency components between
the cutoff frequency and DC. The low-frequency cutoff
of the DC cancellation loop is set by an external capac-
itor connected between CZ_+ and CZ_-.
The MAX3822 incorporates a chatter-free loss-of-power
function that is used to determine if the input signal has
dropped below the programmed threshold level. The
power detector is implemented by comparing the DC-
rectified output of the first gain stage to the pro-
grammed loss-of-power threshold.
The threshold control circuitry enables programming of
LOP_ assert and deassert reference voltages by using
one external resistor, R
er guarantees a voltage at V
The external resistor (R
this voltage into a current. The current through this
resistor sets the power threshold level for the device
(see Typical Operating Characteristics, Loss-of-Power
Threshold Level vs. R
Power Detection and Threshold Control
50Ω
TH
TH
TH
).
) connected to GND converts
(Figure 4). An internal amplifi-
TH
of approximately 0.5V.