MAX9969BDCCQ+TD Maxim Integrated, MAX9969BDCCQ+TD Datasheet - Page 28

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MAX9969BDCCQ+TD

Manufacturer Part Number
MAX9969BDCCQ+TD
Description
Interface - Specialized
Manufacturer
Maxim Integrated
Series
MAX9969r
Datasheet

Specifications of MAX9969BDCCQ+TD

Product Type
ATE Driver/Comparator
Maximum Operating Temperature
+ 70 C
Package / Case
TQFP-100 EP
Minimum Operating Temperature
0 C
Table 5. Shift Register Functions
Dual, Low-Power, 1200Mbps ATE
Driver/Comparator with 35mA Load
The MAX9969 supplies a temperature output signal,
TEMP, that asserts a 3.33V nominal output voltage at a
+70°C (343K) die temperature. The output voltage
changes proportionally with temperature at 10mV/°C.
Under normal circumstances, the MAX9969 requires
heat removal through the exposed pad by use of an
external heat sink. The exposed pad is electrically at
V
isolated.
Power dissipation is highly dependent upon the appli-
cation. The Electrical Characteristics table indicates
power dissipation under the condition that the source
28
BIT
EE
D7
D6
D5
D4
D3
D2
D1
D0
potential, and must be either connected to V
______________________________________________________________________________________
LLEAK
TMSEL
NAME
CDIFF
LDDIS
CH1
CH2
SC1
SC0
Channel 1 Write Enable. Set to 1 to update the
control byte for channel 1. Set to 0 to make no
changes to channel 1.
Channel 2 Write Enable. Set to 1 to update the
control byte for channel 2. Set to 0 to make no
changes to channel 2.
Low-Leakage Select. Set to 1 to put driver,
load, and clamps in low-leakage mode.
Comparators remain active in low-leakage
mode, but at reduced speed. Set to 0 for
normal operation.
Termination Select. Driver Termination Select
Bit. Set to 1 to force the driver output to the
DTV_ voltage when RCV_ = 1 (term mode). Set
to 0 to place the driver into high-impedance
mode when RCV_ = 1 (high-Z). See Table 1.
Driver Slew Rate Select. SC1 and SC0 set the
driver slew rate. See Table 2.
Differential Comparator Enable. Set to 1 to
enable the differential comparators and
disable the CH_ window comparators. Set to 0
to enable the CH_ window comparators and
disable the differential comparators. See
Tables 3a and 3b.
Load D i sab l e. S et LD D IS to 1 to d i sab l e the
l oad . S et to 0 for nor m al op er ati on. S ee Tab l e 4.
Temperature Monitor
DESCRIPTION
Heat Removal
EE
or
and sink currents are programmed to 0mA. Maximum
dissipation occurs when the source and sink currents
are both at 35mA, the V
voltage range (-1.5V or +6.5V), and the diode bridge is
fully commutated. Under these conditions, the addition-
al power dissipated (per channel) is:
If DUT_ is sourcing current:
If DUT_ is sinking current:
DUT_ sources the programmed (low) current when
V
through the outside of the diode bridge and the source
(low) current source to V
rent is greatly reduced by the class AB load architecture.
DUT_ sinks the programmed (high) current when V
< V
the sink (high) current source and the outside of the
diode bridge to DUT_. The programmed source current
is greatly reduced by the class AB architecture.
θ
mately 1°C/W to 2°C/W. Die temperature is thus highly
dependent upon the heat removal techniques used in
the application. Maximum total power dissipation
occurs under the following conditions:
• V
• V
• I
• Load enabled
• V
• V
Under these extreme conditions, the total power dissi-
pation is 3.9W typical and 4.4W maximum. If the die
temperature cannot be maintained at an acceptable
level under these conditions, use software clamping to
limit the load output currents to lower values and/or
reduce the supply voltages.
Bypass all V
capacitors, and use bulk bypassing of at least 10µF on
each supply.
TRANSISTOR COUNT: 5284
PROCESS: Bipolar
JC
DUT_
SOURCE
CC
EE
DUT_
COM_
COM_
of the exposed-pad package is very low, approxi-
= -5.25V
= +10.5V
> V
= -1.5V
Power-Supply Considerations
. The path of the current is from V
= +0.5V
COM_
= I
P
CC
SINK
D
P
D
= (V
. The path of the current is from DUT_
and V
= (V
= 35mA for both channels
DUT_
CC
EE
EE
DUT
- V
- V
power input pins with 0.01µF
. The programmed sink cur-
DUT_
Chip Information
EE
_ is at an extreme of the
) x I
) x I
SOURCE
SINK
CC
through
DUT_

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