MAX9969BDCCQ+TD Maxim Integrated, MAX9969BDCCQ+TD Datasheet - Page 27

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MAX9969BDCCQ+TD

Manufacturer Part Number
MAX9969BDCCQ+TD
Description
Interface - Specialized
Manufacturer
Maxim Integrated
Series
MAX9969r
Datasheet

Specifications of MAX9969BDCCQ+TD

Product Type
ATE Driver/Comparator
Maximum Operating Temperature
+ 70 C
Package / Case
TQFP-100 EP
Minimum Operating Temperature
0 C
When DUT_ is driven with a high-speed signal while
LLEAK is asserted, the leakage current momentarily
increases beyond the limits specified for normal opera-
Figure 4. Serial Interface
Figure 5. Serial-Interface Timing
SCLK
THR
RST
DIN
CS
SCLK
DIN
20kΩ
CS
MAX9969
V
THRINT
0 - 4
5
7
7
______________________________________________________________________________________
= 1.25V
D
ENABLE
D
ENABLE
ENABLE
t
SET
CH
F/F
F/F
CHANNEL 1 MODE BITS
t
Q
Q
CSS0
0
SC0, SC1
TMSEL,
LDDIS,
CDIFF,
5
D6
1
Driver/Comparator with 35mA Load
LLEAK
SHIFT REGISTER
2
1
3
0 - 4
5
6
6
Dual, Low-Power, 1200Mbps ATE
t
DS
4
D
ENABLE
D
ENABLE
D5
5
SET
F/F
F/F
t
DH
CHANNEL 2 MODE BITS
6
Q
Q
SC0, SC1
TMSEL,
LDDIS,
CDIFF,
7
5
LLEAK
D4
1
t
CL
D3
tion. The low-leakage recovery specification in the
Electrical Characteristics table indicates device behav-
ior under this condition.
A CMOS-compatible serial interface controls the
MAX9969 modes (Figure 4 and Table 5). Control data
flow into an 8-bit shift register (MSB first) and are
latched when CS is taken high, as shown in Figure 5.
Latches contain 6 control bits for each channel of the
dual pin driver. Data from the shift register are loaded
to either or both of the latches as determined by bits D6
and D7. When CDIFF = 1, its effect is independent of
bits D6 and D7. The control bits, in conjunction with
external inputs DATA_ and RCV_, manage the features
of each channel, as shown in Tables 1 and 2. RST sets
LLEAK = 1 for both channels, forcing them into low-
leakage mode. All other bits are unaffected. At power-
up, hold RST low until V
Analog control input THR sets the threshold for the
input logic, allowing operation with CMOS logic as low
as 0.9V. Leaving THR unconnected results in a nominal
threshold of 1.25V from an internal reference, providing
compatibility with 2.5V to 3.3V logic.
The MAX9969 is pin compatible with the MAX9967 with
minor changes.
• No PMU force/sense connection on the MAX9969
• Different common-mode ranges for control inputs
• MAX9967 comparator outputs additionally support
• Different serial interface bit structures
open emitter
D2
Serial Interface and Device Control
D1
t
CSH1
CC
MAX9967 Compatibility
D0
and V
t
CSS1
EE
t
CSWH
have stabilized.
27

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