ST8024LTR STMicroelectronics, ST8024LTR Datasheet - Page 21

• Manufacturer Part Number: ST8024LTR
• Description: Interface - Specialized Smart card interface 3V or 5V 26 MHz
• Manufacturer: STMicroelectronics

Specifications of ST8024LTR

• Product Category: Interface - Specialized
• Rohs: yes
• Product Type: Smart Card Interface
• Operating Supply Voltage: 2.7 V to 6.5 V
• Supply Current: 1.2 mA
• Maximum Power Dissipation: 0.56 W
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TSSOP-20
• Minimum Operating Temperature: - 25 C

ST8024L
6.4
6.5
6.6
I/O transceivers
The three data lines I/O, AUX1, and AUX2 are identical. The idle state is realized by both I/O
and I/OUC lines being pulled high via an 11 kΩ resistor (I/O to V
I/O is referenced to V
equal to V
An anti-latch circuit disables the detection of falling edges on the line of the other side, which
then becomes a slave. After a time delay t
on, therefore transmitting the logic 0 present on the master side. When the master side
returns to logic 1, a P transistor on the slave side is turned on during the time delay t
then both sides return to their idle states. This active pull-up feature ensures fast low to high
transitions; it is able to deliver more than 1 mA, at an output voltage of up to 0.9 V
80 pF load. At the end of the active pull-up pulse, the output voltage depends only on the
internal pull-up resistor and the load current. The current to and from the card I/O lines is
limited internally to 15 mA and the maximum frequency on these lines is 1 MHz.
Inactive mode
After a power-on reset, the circuit enters inactive mode. A minimum number of circuits are
active while waiting for the microcontroller to start a session:
Activation sequence
After power-on and after the internal pulse width delay, the system microcontroller can
check the presence of a card using the signals OFF and CMDVCC, as shown in
If the card is in the reader (this is the case if PRES or PRES is active), the system
microcontroller can start a card session by pulling CMDVCC low. The following sequence
then occurs (see
– All card contacts are inactive (approximately 200 Ω to GND)
– Pins I/OUC, AUX1UC, and AUX2UC are in the high impedance state (11 kΩ pull-up
– Voltage generators are stopped
– XTAL oscillator is running
– Voltage supervisor is active
– The internal oscillator is running at its low frequency.
1. CMDVCC is pulled low and the internal oscillator changes to its high frequency (t
2. The step-up converter is started (between t
3. V
T is 64 times the period of the internal oscillator (approximately 25 µs).
4. I/O, AUX1, and AUX2 are enabled (t
moment).
5. CLK is applied to the C3 contact of the card reader (t
6. RST is enabled (t
resistor to V
CC
DD
rises from 0 to 5 V (or 1.8 V, 3 V) with a controlled slope (t
. The first side of the transceiver to receive a falling edge becomes the master.
Figure
DD
CC
). Applies only to SO-28 and TSSOP-28 packages.
, and pin I/OUC to V
6):
5
= t
1
Doc ID 17709 Rev 5
+ 7T).
d(edge)
DD
3
= t
, therefore allowing operation when V
1
, an N transistor on the slave side is turned
+ 4T) (these were pulled low until this
0
and t
1
).
4
).
CC
and I/OUC to V
Functional description
2
= t
1
+ 1.5 x T) where
Table
CC
DD
CC
, into an
PU
). Pin
is not
22.
21/35
and
0
).