MAX7321AEE-T Maxim Integrated, MAX7321AEE-T Datasheet - Page 7

• Manufacturer Part Number: MAX7321AEE-T
• Description: Interface - I/O Expanders
• Manufacturer: Maxim Integrated
• Series: MAX7321r

Table 2. Read and Write Access to Eight-Port Expander Family
The RST input voids any I
MAX7321, forcing the MAX7321 into the I
dition. A reset does not affect the interrupt output (INT).
When the serial interface is idle, the MAX7321 automat-
ically enters standby mode, drawing minimal supply
current.
Address inputs AD0 and AD2 determine the MAX7321
slave address, set the power-up I/O state for the ports,
and select which inputs have pullup resistors. Internal
pullups and power-up default states are set in groups
of four
and MAX7323 use a different range of slave addresses
(110xxxx) than the MAX7320 (101xxxx) (Table 2).
The MAX7321 slave address is determined on each I
transmission, regardless of whether the transmission is
actually addressing the MAX7321. The MAX7321 distin-
guishes whether address inputs AD2 and AD0 are con-
nected to SDA or SCL instead of fixed logic levels V+ or
GND during this transmission. This means that the
MAX7319
MAX7320
MAX7321
MAX7322
MAX7323
MAX7328
MAX7329
PART
Slave Address, Power-Up Default Logic
(Table 3). The MAX7319, MAX7321, MAX7322,
I
ADDRESS
Levels, and Input Pullup Selection
2
110xxxx
101xxxx
110xxxx
110xxxx
110xxxx
0100xxx
0111xxx
C SLAVE
I
2
_______________________________________________________________________________________
C Port Expander with 8 Open-Drain I/Os
INPUTS
Up to 8
Up to 4
Up to 8
Up to 8
—
8
4
2
C transaction involving the
INTERRUPT
MASK
Standby Mode
Yes
Yes
—
—
—
—
—
2
C STOP con-
RST Input
OUTPUTS
Up to 8
Up to 4
Up to 8
Up to 8
OPEN-
DRAIN
—
—
—
2
C
MAX7321 slave address can be configured dynamical-
ly in the application without cycling the device supply.
On initial power-up, the MAX7321 cannot decode
address inputs AD0 and AD2 fully until the first I
transmission. AD0 and AD2 initially appear to be con-
nected to V+ or GND. This is important because the
address selection is used to determine the power-up
logic state and whether pullups are enabled. However,
at power-up, the I
are high impedance at the pins of every device (master
or slave) connected to the bus, including the MAX7321.
This is guaranteed as part of the I
Therefore, address inputs AD2 and AD0 that are con-
nected to SDA or SCL normally appear at power-up to
be connected to V+. The power-up logic uses AD0 to
select the power-up state and whether pullups are
enabled for ports P3–P0, and AD2 for ports P7–P4. The
rule is that a logic-high, SDA, or SCL connection
selects the pullups and sets the default logic state to
high. A logic-low deselects the pullups and sets the
default logic state to low (Table 3). The port configura-
tion is correct on power-up for a standard I
ration, where SDA or SCL are pulled up to V+ by the
external I
OUTPUTS
PUSH-
PULL
—
—
—
—
8
4
4
2
C pullup resistors.
I
<O7, O6 outputs,
2
<I7–I0 interrupt
<port outputs>
C DATA WRITE
I5–I2 interrupt
mask, O1, O0
<O7–O0 port
<P7–P0 port
<P7–P0 port
<P7–P0 port
outputs>
outputs>
outputs>
outputs>
outputs>
mask>
2
C SDA and SCL bus interface lines
<O7, O6, P5–P2, O1, O0 port
<0, 0, P5–P2 transition flags,
<O7, O6, I5–I2, O1, O0 port
<0, 0, I5–I2 transition flags,
<P7–P0 transition flags>
<I7–I0 transition flags>
<O7-O0 port inputs>
<P7–P0 port inputs>
<P7–P0 port inputs>
<P7–P0 port inputs>
<I7–I0 port inputs>
I
2
C DATA READ
2
C specification.
inputs>
inputs>
0, 0>
0, 0>
2
C configu-
2
C
7