MAX7321AEE-T Maxim Integrated, MAX7321AEE-T Datasheet - Page 12

• Manufacturer Part Number: MAX7321AEE-T
• Description: Interface - I/O Expanders
• Manufacturer: Maxim Integrated
• Series: MAX7321r

A write to the MAX7321 starts with the master transmit-
ting the MAX7321’s slave address with the R/W bit set
low. The MAX7321 acknowledges the slave address,
and samples the ports (takes a snapshot) during
acknowledge. INT goes high (high impedance if an
external pullup resistor is not fitted) during the slave
acknowledge. Typically, the master proceeds to trans-
mit 1 or more bytes of data. The MAX7321 acknowl-
edges these subsequent bytes of data and updates the
I/O ports with each new byte until the master issues a
STOP condition
The MAX7321’s SDA, SCL, AD0, AD2, RST, INT, and I/O
ports P0–P7 are overvoltage protected to +6V indepen-
dent of V+. This allows the MAX7321 to operate from a
lower supply voltage, such as +3.3V, while the I
face and/or any of the eight I/O ports are driven as inputs
driven from a higher logic level, such as +5V.
The MAX7321 can operate from a higher supply volt-
age, such as +3V, while the I
of the I/O ports P0–P7 are driven from a lower logic
level, such as +2.5V. Apply a minimum voltage of 0.7 x
V+ to assert a logic-high on any I/O port. For example,
a MAX7321 operating from a +5V supply may not rec-
ognize a +3.3V nominal logic-high. One solution for
input-level translation is to drive MAX7321 I/Os from
open-drain outputs. Use a pullup resistor to V+ or a
I
Figure 8. Writing to the MAX7321
12
2
C Port Expander with 8 Open-Drain I/Os
INTERNAL WRITE
______________________________________________________________________________________
FROM PORT
DATA OUT
TO PORT
Port Input and I
SDA
SCL
Translation from Higher or Lower
Applications Information
(Figure 8).
START CONDITION
S
1
2
SLAVE ADDRESS
3
S = START CONDITION
P = STOP CONDITION
2
4
Writing to the MAX7321
C interface and/or some
2
5
C Interface Level
Logic Voltages
6
7
R/W
0
8
A
SHADED = SLAVE TRANSMISSION
N = NOT ACKNOWLEDGE
2
C inter-
DATA TO PORT
DATA 1
higher supply to ensure a high logic voltage greater
than 0.7 x V+.
The open-drain output architecture allows for level
translation to higher or lower voltages than the
MAX7321’s supply. Use an external pullup resistor on
any output to convert the high-impedance logic-high
condition to a positive voltage level. The resistor can be
connected to any voltage up to +6V, and the resistor
value chosen to ensure no more than 20mA is sunk in
the logic-low condition. For interfacing CMOS inputs, a
pullup resistor value of 220kΩ is a good starting point.
Use a lower resistance to improve noise immunity, in
applications where power consumption is less critical,
or where a faster rise time is needed for a given capac-
itive load.
Each of the I/O ports P0–P7 has a protection diode to
GND (Figure 9). When a port is driven to a voltage
lower than GND, the protection diode clamps the volt-
age to a diode drop below GND.
Each of the I/O ports P0–P7 also has a 40kΩ (typ) pullup
resistor that can be enabled or disabled. When a port is
driven to a voltage higher than V+
pullup enable switch conducts and the 40kΩ pullup
resistor is enabled. When the MAX7321 is powered
down (V+ = 0), each I/O port appears as a 40kΩ resistor
in series with a diode connected to zero. I/O ports are
protected to +6V under any of these circumstances
(Figure 9).
t
t
PV
PV
Port-Output Port-Level Translation
A
DATA TO PORT
DATA 1 VALID
DATA 2
,
the body diode of the
t
t
PV
PV
A
DATA 2 VALID