TDA19989AET/C185 NXP Semiconductors, TDA19989AET/C185 Datasheet
TDA19989AET/C185
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TDA19989AET/C185 Summary of contents
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TDA19989 150 MHz pixel rate HDMI 1.3 transmitter with 3 × 8-bit video inputs, HDCP and CEC support Rev. 01 — 15 February 2010 1. General description TDA19989 is a very low power and very small size High-Definition Multimedia Interface ...
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... NXP Semiconductors 2 I S/PDIF YCbCr Fig 1. 2. Features Compliance: DVI 1.0 HDMI 1.3a EIA/CEA-861B CEC (HDMI 1.3) SimplayHD HDCP 1.3 Video: xvYCC HDMI 1.3 feature Video formats with a pixel rate up to 150 MHz: RGB YCbCr YCbCr semi-planar YCbCr ITU656 Maximum resolution: 1080p for TV 1600 × ...
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... NXP Semiconductors Internal SHA-1 calculation System operation: Master DDC-bus interface for EDID read Controllable via I Downstream availability through the use of hot plug detect (HPD) and receiver detection (RxSense) Deals with multiple levels of receivers and repeaters Package: TFBGA64 Size 4.5 × 4.5 × 0.95 mm Power management: External voltage supplies 1 ...
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AUDIO PROCESSING FIFO ACLK BUFFER AUDIO AP1 CAPTURE PROCESSING WS CTS/N PLL BLOCK CLOCK VCLK MANAGEMENT 3 × 8-bit RGB or YCbCr × 12-bit YCbCr semi-planar VSYNC/VREF HSYNC/VREF VIDEO ...
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... NXP Semiconductors 6. Pinning information 6.1 Pinning Fig 3. 6.2 Pin description Table 2. Symbol ACLK AP0 AP1 HPD EXT_SWING DSDA DSCL VCLK HSYNC/HREF VSYNC/VREF DE/FREF CSCL CSDA INT TX0− TX0+ TX1− TDA19989_1 Preliminary data sheet HDMI 1.3 transmitter with HDCP and CEC support ball A1 ...
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... NXP Semiconductors Table 2. Symbol TX1+ TX2− TX2+ TXC− TXC+ CEC OSC_IN/AP3 AP2 VPA[0] VPA[1] VPA[2] VPA[3] VPA[4] VPA[5] VPA[6] VPA[7] VPB[0] VPB[1] VPB[2] VPB[3] VPB[4] VPB[5] VPB[6] VPB[7] VPC[0] VPC[1] VPC[2] VPC[3] VPC[4] VPC[5] VPC[6] VPC[7] V DDA(TMDS)(1V8) V DDD(IO)(1V8) ...
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... NXP Semiconductors Table 2. Symbol V DDDC V SSD V SSA [ power supply ground input output. 7. Functional description TDA19989 is designed to convert digital data (video and audio) provided by Set-Top Boxes (STB), Digital Video Camera (DVC), Digital Still Camera (DSC), Portable Multimedia Player (PMP) or DVD into an HDMI output, which can be used with either an HDMI or DVI input ...
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... NXP Semiconductors 7.2 Video input formatter 7.2.1 Description TDA19989 has three video input ports VPA[0] to VPA[7], VPB[0] to VPB[7] and VPC[0] to VPC[7]. TDA19989 can accept any of the following video input modes (see • RGB, with 8-bit for each component • YCbCr with 8-bit for each component • ...
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... NXP Semiconductors Table 3. Internal assignment Internal port VP[11] VP[10] VP[9] VP[8] VP[7] VP[6] VP[5] VP[4] VP[3] VP[2] VP[1] VP[0] The device can swap and invert, in the event of a little endian stream, the incoming video data using I 00h) to match the expectation of the video processing block. of SWAP_A[2:0] of VIP_CNTRL_0 register, whose function is to map the 4 MSBs VP[23:20] to the incoming video port ...
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... NXP Semiconductors Table 4. Video input swap to VP[23:20] External SWAP_A[2:0] assignment selector value Pin Pin number name F3 VPC[7] 000b F2 VPC[6] F1 VPC[5] G1 VPC[4] G2 VPC[3] 001b G3 VPC[2] H2 VPC[1] H3 VPC[0] C3 VPB[7] 010b C2 VPB[6] D3 VPB[5] D2 VPB[4] D1 VPB[3] 011b E1 VPB[2] E2 VPB[1] E3 VPB[0] A4 VPA[7] 100b B4 VPA[6] A3 VPA[5] B3 VPA[4] A2 VPA[3] 101b ...
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... NXP Semiconductors Table 5. Bit setting MIRR_A = 1 SWAP_A[2: MIRR_B = 1 SWAP_B[2: MIRR_C = 1 SWAP_C[2: MIRR_D = 1 SWAP_D[2: MIRR_E = 1 SWAP_E[2: MIRR_F = 1 SWAP_F[2: When input ports are not used possible to deactivate them via the I appropriate set of registers ENA_VP_0, ENA_VP_1 and ENA_VP_2 on page 00h. TDA19989_1 Preliminary data sheet HDMI 1 ...
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Input format mappings Table 6 gives more information concerning input format supported. Table 6. Inputs of video input formatter Color Format Channels Sync type Rising space edge × 8-bit RGB external X embedded ...
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... NXP Semiconductors 7.2.3.1 RGB external synchronization (rising edge) RGB (3 × 8-bit) external synchronization input (rising edge) mapping Table 7. Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 45h; VIP_CNTRL_2 = 01h. Video port A Video port B Pin RGB Pin VPA[0] B[0] VPB[0] VPA[1] B[1] VPB[1] VPA[2] B[2] VPB[2] VPA[3] B[3] VPB[3] ...
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... NXP Semiconductors VCLK HSYNC/HREF CONTROL VSYNC/VREF INPUTS DE/FREF VPA[0] to VPA[ VPB[0] to VPB[7] Y [7:0] 0 VPC[0] to VPC[7] Cr [7: could also be generated from HSYNC/HREF and VSYNC/VREF. Fig 6. Pixel encoding YCbCr external synchronization input (rising edge) 7.2.3.3 YCbCr ITU656-like external synchronization (rising edge) Table 9 ...
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... NXP Semiconductors 7.2.3.4 YCbCr ITU656-like external synchronization (double edge) Table 10. YCbCr ITU656-like external synchronization input (double edge) mapping Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 50h; VIP_CNTRL_2 = 00h. Video port A Pin YCbCr (ITU656-like) VPA[0] Cb[0] Y [0] Cr[0] 0 VPA[1] Cb[1] Y [1] Cr[1] 0 VPA[2] Cb[2] Y [2] Cr[2] 0 VPA[3] Cb[3] Y [3] Cr[3] 0 VPA[4] - ...
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... NXP Semiconductors VCLK VPB[0] to VPB[7]; Cb [11:0] 0 VPA[0] to VPA[3] Fig 9. Pixel encoding YCbCr ITU656-like embedded synchronization input (rising edge) 7.2.3.6 YCbCr ITU656-like embedded synchronization (double edge) Table 12. YCbCr ITU656-like embedded synchronization input (double edge) mapping Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 50h; VIP_CNTRL_2 = 00h. ...
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... NXP Semiconductors 7.2.3.7 YCbCr semi-planar external synchronization (rising edge) Table 13. YCbCr semi-planar external synchronization input (rising edge) mapping Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 50h; VIP_CNTRL_2 = 14h. Video port A Video port B Pin YCbCr Pin semi-planar VPA[0] Y [0] Y [0] VPB[ VPA[1] ...
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... NXP Semiconductors VCLK VPB[0] to VPB[7]; Y [11:0] 0 VPA[0] to VPA[3] VPC[0] to VPC[7]; Cb [11:0] 0 VPA[4] to VPA[7] Fig 12. Pixel encoding YCbCr semi-planar embedded synchronization input (rising edge) 7.2.4 Synchronization TDA19989 can be synchronized with extraction of the sync information from embedded sync (SAV/EAV) codes inside the video stream or with external HSYNC/VSYNC inputs. ...
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... NXP Semiconductors Table 15. Input Color space YCbCr 7.4 Upsampler The incoming YCbCr × 12-bit) data stream format could be upsampled into YCbCr × 8-bit) data stream by repeating or linearly interpolating the chrominance pixels. 7.5 Color space converter The color space converter is used to convert input video data from one type to another color space (e ...
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... NXP Semiconductors TDA19989 can carry audio in I S/PDIF format through one audio pin named AP1. S/PDIF or I selected via the S-bus. Table 16. Audio port AP0 AP1 AP2 AP3 ACLK All audio ports are LV-CMOS 1.8 V compatible and LV-CMOS 3.3 V tolerant possible to deactivate unused ports via I and clock inputs ...
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... NXP Semiconductors word select a. Philips format. word select b. Left justified format. word select c. Right justified format. Fig 13 The I S-bus input interface can receive up to 24-bit wide audio samples via the serial data input with a clock frequency of at least 32 times the input sample frequency f Audio samples with a precision better than 24-bit are truncated to 24-bit ...
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... NXP Semiconductors 7.8.3 Audio port internal assignment The aim of the internal audio input assignment is to internally map any of the incoming data from the audio port AP1 or AP2 to I setting the appropriate I Fig 14. Audio input swap to I 7.9 Power management TDA19989 HDMI and CEC cores can be independently powered down by the I register ...
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... NXP Semiconductors 7.10 Interrupt controller Pin INT is used to alert the system microcontroller that a critical event concerning the HDMI or CEC has occurred. The software provided with the device read a status register 2 (I C-bus) to determine which block between HDMI and CEC has caused the interruption before processing it ...
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... NXP Semiconductors Fig 15. As long as the receiver is connected to the transmitter and powered-up, bit RXS_FIL is set to logic 1. As soon as the cable is unplugged or receiver side powered off (assuming in this case that V is switched off), the RxSense generates an interrupt inside TDA19989, changing the CC value of bit RXS_FIL to logic 0 (See unnecessary video content ...
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... NXP Semiconductors 7.11 HDCP processing 7.11.1 High-bandwidth digital content protection TDA19989 contains an HDCP function, which encrypts the transmitted stream content (both video and audio). This function can be enabled and disabled via the I The keys can be stored internally in OTP non-volatile memory or can be loaded via the ...
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... NXP Semiconductors 7.12.2 Clock CEC clock must be running in Sleep mode (with CEC) to wake up TDA19989 using CEC specific message as described in “HDMI specification 1.3a”. CEC module can be clocked using: • External clock: – 12 MHz crystal ± • Internal clock: – FRO (Free Running Oscillator). FRO frequency varies and in the range from 12 ...
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... NXP Semiconductors 7.12.4 Power-On Reset (POR) After power-up, TDA19989 is activated by internal reset from POR module. This is used to set TDA19989 to a known state. 7.12.5 Repeater function TDA19989 can be used in a repeater device according to HDMI 1.3a. 7.13 HDMI core 7.13.1 Output TMDS buffers 7.13.1.1 Digitally controlled signal amplitude The TMDS signal output peak-to-peak voltage (Vswing) is programmable by the software ...
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... NXP Semiconductors 7.14 E-EDID 7.14.1 E-EDID reading As a master interface for the EDID process, the DDC-bus is compliant with the I specification and has the possibility of repeat/start condition to enable quick access to the EDID content, as well as the possibility of reading a large EDID (with the use of segment pointer). ...
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... NXP Semiconductors C-bus interface and register definitions 2 8.1 I C-bus protocol 2 The I C-bus pins CSDA and CSCL are 1.8 V and 3.3 V tolerant. Both Fast mode (400 kHz) and Standard mode (100 kHz) are supported. The registers of TDA19989 can be accessed via the I for those which are confidential. ...
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... NXP Semiconductors The CEC core does not need memory page mechanism due to its reduced number of registers. 8.3 ID version The ID version readable via I and VERSION registers. The ID version value is 212h. 8.4 Clock stretching Clock stretching pauses a transaction by holding the CSCL line LOW. The transaction cannot continue until the line is released HIGH again ...
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... NXP Semiconductors Table 23. Input format …continued L: recommend tield to LOW voltage, e.g. ground Input pins Signal RGB VPB[6] Y[6]/G[6] G[6] VPB[7] Y[7]/G[7] G[7] Video port C VPC[0] Cr[0]/R[0] R[0] VPC[1] Cr[1]/R[1] R[1] VPC[2] Cr[2]/R[2] R[2] VPC[3] Cr[3]/R[3] R[3] VPC[4] Cr[4]/R[4] R[4] VPC[5] Cr[5]/R[5] R[5] VPC[6] Cr[6]/R[6] R[6] VPC[7] Cr[7]/R[7] R[7] 9.1 Timing parameters for video supported TDA19989 supports all EIA/CEA-861B standards and ATSC video input formats. ...
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... NXP Semiconductors Table 24. Timing parameters for EIA/CEA-861B EIA/CEA-861b Format Video code 2880 × 480i 10, 11 2880 × 240p 12, 13 2880 × 240p 12, 13 1440 × 480p 14, 15 1920 × 1080p systems 720 × 576p 17, 18 1280 × 720p 19 1920 × 1080i 20 1440 × ...
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... NXP Semiconductors 9.2 Timing parameters for PC standards supported TDA19989 can support all major PC Standards up to 150 MHz. Table 26. Timing parameters for PC standards below 150 MHz Standard Format 640 × 350p 640 × 400p 720 × 400p 640 × 480p 0.31M3 VGA 640 × 480p 640 × ...
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... NXP Semiconductors Table 26. Timing parameters for PC standards below 150 MHz Standard Format 1400 × 1050p 1.47M3-R 1400 × 1050p 1.47M3 1440 × 900p 1.29MA-R 1440 × 900p 1.29MA 1440 × 900p 1680 × 1050p 1.76MA-R 1680 × 1050p 1.76MA 10. Limiting values Table 27 ...
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... NXP Semiconductors 12. Static characteristics Table 29. Supplies − ° ° +85 C; without HDCP; unless otherwise specified. amb Symbol Parameter V core digital supply voltage DDDC V TMDS analog supply voltage (1.8 V) DDA(TMDS)(1V8) V PLL analog supply voltage (1.8 V) DDA(PLL)(1V8) V analog supply voltage (1.8 V) DDA(1V8) V I/O digital supply voltage (1 ...
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... NXP Semiconductors Table 30. Digital inputs and outputs − ° ° +85 C; unless otherwise specified. amb Symbol Parameter Not 5 V tolerant CMOS 1.8 V and CMOS 3.3 V tolerant digital input pins HSYNC, VSYNC, APn, ACLK, VPA[n], VPB[n], VPC[n], VCLK LOW-level input voltage ...
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... NXP Semiconductors 13. Dynamic characteristics Table 31. Timing characteristics − ° ° +85 C; unless otherwise specified. amb Symbol Parameter Clock input: pin VCLK f maximum clock frequency clk(max) t data input set-up time su(D) t data input hold time h(D) δ clock duty cycle clk f clock frequency ...
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... NXP Semiconductors DE, HSYNC, VSYNC DE, HSYNC, VSYNC Fig 18. Set-up and hold time definition diagram for single-edge clock mode VPA[0] to VPA[7] VPB[0] to VPB[7] VPC[0] to VPC[7] DE, HSYNC, VSYNC Fig 19. Set-up and hold time definition diagram for double-edge clock mode TDA19989_1 Preliminary data sheet HDMI 1.3 transmitter with HDCP and CEC support ...
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... NXP Semiconductors 14. Application information 14.1 Transmitter connection with external world Figure 20 be part of a repeater application as described in “HDMI specification 1.3a”. Fig 20. Connecting TDA19989 transmitter using external clock source Fig 21. Connecting TDA19989 transmitter using internal FRO for CEC TDA19989_1 Preliminary data sheet HDMI 1.3 transmitter with HDCP and CEC support ...
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... NXP Semiconductors 15. Package outline TFBGA64: plastic thin fine-pitch ball grid array package; 64 balls ball A1 index area ball index area DIMENSIONS (mm are the original dimensions) UNIT max 1.10 0.30 0.80 mm nom 0.95 0.25 0.70 min 0.85 0.20 0.65 OUTLINE VERSION IEC SOT962 Fig 22. Package outline SOT962-3 (TFBGA64) ...
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... NXP Semiconductors 16. Abbreviations Table 32. Acronym AC3 ACP ACR ATSC AV BOM CEA CEC CTS/N DDC DDR DE DSC DTS DTV DVC DVD DVI EAV EDID E-EDID EIA FCDM FIFO FREF FRO HBM HDCP HDMI HPD HREF HSYNC LSB LV-CMOS MPEG MSB OTP PC PCB ...
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... NXP Semiconductors Table 32. Acronym PCM PLL PMP POR RGB SAV SDR SMPTE S/PDIF STB TMDS UM PC UXGA60 VHREF VREF VSYNC YCbCr WS 17. Revision history Table 33. Revision history Document ID Release date TDA19989_1 20100215 TDA19989_1 Preliminary data sheet HDMI 1.3 transmitter with HDCP and CEC support Abbreviations … ...
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... Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ ...
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... NXP Semiconductors 20. Tables Table 1. Ordering information . . . . . . . . . . . . . . . . . . . . .3 Table 2. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .5 Table 3. Internal assignment . . . . . . . . . . . . . . . . . . . . . .8 Table 4. Video input swap to VP[23:20 .10 Table 5. TDA19989 input/output capability . . . . . . . . . . 11 Table 6. Inputs of video input formatter . . . . . . . . . . . . .12 Table 7. RGB (3 ¥ 8-bit) external synchronization input (rising edge) mapping . . . . . . . . . . . . . . . . . . .13 Table 8. YCbCr ¥ 8-bit) external synchronization input (rising edge) mapping ...
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... NXP Semiconductors 21. Figures Fig 1. TDA19989 high-level block diagram . . . . . . . . . . .2 Fig 2. TDA19989 Block diagram . . . . . . . . . . . . . . . . . . .4 Fig 3. Pin configuration (TFBGA64 Fig 4. Internal assignment of VP[23:0 Fig 5. Pixel encoding RGB external synchronization input (rising edge .13 Fig 6. Pixel encoding YCbCr external synchronization input (rising edge .14 Fig 7. ...
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... NXP Semiconductors 22. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 Functional description . . . . . . . . . . . . . . . . . . . 7 7.1 System clock . . . . . . . . . . . . . . . . . . . . . . . . . . 7 7.2 Video input formatter . . . . . . . . . . . . . . . . . . . . 8 7.2.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 7.2.2 Internal assignment . . . . . . . . . . . . . . . . . . . . . 8 7.2.3 Input format mappings . . . . . . . . . . . . . . . . . . 12 7.2.3.1 RGB external synchronization (rising edge ...