SC16IS762IBS-F NXP Semiconductors, SC16IS762IBS-F Datasheet - Page 40

• Manufacturer Part Number: SC16IS762IBS-F
• Description: UART Interface IC I2C/SPI-UARTBRIDGE W/IRDA AND GPIO
• Manufacturer: NXP Semiconductors
• Type: RS-232 or RS-485 or IrDAr

Specifications of SC16IS762IBS-F

• Product Category: UART Interface IC
• Rohs: yes
• Number Of Channels: 2
• Data Rate: 5 Mbps
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.3 V
• Supply Current: 6 mA
• Maximum Operating Temperature: + 95 C
• Minimum Operating Temperature: - 40 C
• Package / Case: HVQFN-32
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 2.5 V, 3.3 V
• Factory Pack Quantity: 1500
• Part # Aliases: SC16IS762IBS,128

NXP Semiconductors
SC16IS752_SC16IS762
Product data sheet
Fig 18. Master writes to slave
Fig 19. Master read from slave
(1) See
(1) See
S
White block: host to SC16IS752/SC16IS762
Grey block: SC16IS752/SC16IS762 to host
White block: host to SC16IS752/SC16IS762
Grey block: SC16IS752/SC16IS762 to host
SLAVE ADDRESS
Table 33
Table 33
S
for additional information.
for additional information.
SLAVE ADDRESS
The register read cycle (see
sending a slave address with the direction bit set to WRITE with a following subaddress.
Then, in order to reverse the direction of the transfer, the master issues a Repeated
START followed again by the device address, but this time with the direction bit set to
READ. The data bytes starting at the internal subaddress will be clocked out of the device,
each followed by a master-generated acknowledge. The last byte of the read cycle will be
followed by a negative acknowledge, signalling the end of transfer. The cycle is
terminated by a STOP signal.
Table 33.
Bit
7
6:3
2:1
0
W
Register address byte (I
Name
-
A[3:0]
CH1, CH0
-
A
All information provided in this document is subject to legal disclaimers.
W
REGISTER ADDRESS
Dual UART with I
Rev. 9 — 22 March 2012
A
REGISTER ADDRESS
Figure
Function
not used
UART’s internal register select
Channel select.
not used
00 = channel A
01 = channel B
10 = reserved
11 = reserved
2
(1)
C)
19) commences in a similar manner, with the master
A
SC16IS752; SC16IS762
2
C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
nDATA
(1)
S
A
SLAVE ADDRESS
A
nDATA
LAST DATA
A
002aab047
R
© NXP B.V. 2012. All rights reserved.
P
NA
A
002aab048
P
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