MAX3107ETG/V+ Maxim Integrated, MAX3107ETG/V+ Datasheet - Page 43

• Manufacturer Part Number: MAX3107ETG/V+
• Description: UART Interface IC UART
• Manufacturer: Maxim Integrated

Specifications of MAX3107ETG/V+

• Number Of Channels: 1
• Data Rate: 24 Mbps
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 1.71 V
• Supply Current: 4 mA

Maxim Integrated
CLKSource—Clock Source Register
Bit 7: CLKtoRTS
Set the CLKtoRTS bit to 1 to route the baud-rate generator (16x baud rate) output clock to RTS/CLKOUT. The clock
frequency is a factor of 16x, 8x, or 4x of the baud rate, depending on the BRGConfig[5:4] settings.
Bits 6 and 5: No Function
Bit 4: ClockEn
Set the ClockEn bit high to enable an external clocking (crystal or clock generator at XIN). Set the ClockEn bit to 0 to
disable clocking.
Bit 3: PLLBypass
Set the PLLBypass bit high to enable bypassing the internal PLL and predivider.
Bit 2: PLLEn
Set the PLLEn bit high to enable the internal PLL. If PLLEn is set low, the internal PLL is disabled.
Bit 1: CrystalEn
Set the CrystalEn bit high to enable the crystal oscillator. When using an external clock source at XIN, CrystalEn must
be set low.
Bit 0: No Function
Always keep Bit 0 at logic 0.
RevID—Revision Identification Register
Bit 7–0: Bit[7:0]
The RevID register indicates the revision number of the MAX3107 silicon, starting with 0xA1. This can be used during
software development.
ADDRESS:
MODE:
ADDRESS:
MODE:
RESET
RESET
NAME
NAME
BIT
BIT
CLKtoRTS
Bit7
7
0
7
1
0x1E
R/W
0x1F
R
Bit6
SPI/I
—
6
0
6
0
2
Bit5
—
5
0
5
1
C UART with 128-Word FIFOs
ClockEn
Bit4
4
0
4
0
PLLBypass
Bit3
3
1
3
0
PLLEn
Bit2
2
0
2
0
MAX3107
CrystalEn
Bit1
1
0
1
0
Bit0
—
0
0
0
1
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