MAX3881ECB-D Maxim Integrated, MAX3881ECB-D Datasheet
MAX3881ECB-D
Specifications of MAX3881ECB-D
Related parts for MAX3881ECB-D
MAX3881ECB-D Summary of contents
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... Exceeds ANSI, ITU, and Bellcore Specifications o Additional High-Speed Input Facilitates System Loopback Diagnostic Testing o 2.488Gbps Serial to 155Mbps Parallel Conversion o Differential PECL Clock Output o Single-Ended PECL Data Outputs o Tolerates >2000 Consecutive Identical Digits o Loss-of-Lock Indicator PART MAX3881ECB *Exposed pad Applications TOP VIEW GND 1 FIL+ 2 FIL- ...
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SDH/SONET 1:16 Deserializer with Clock Recovery ABSOLUTE MAXIMUM RATINGS Positive Supply Voltage (V )...............................-0.5V to +7.0V CC Input Voltage Level (SDI+, SDI-, SLBI+, SLBI-) ...............................(V CC Input Current Level (SDI+, SDI-, SLBI+, SLBI-)................±10mA Voltage at LOL, SIS, PHADJ+, ...
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Deserializer with Clock Recovery AC ELECTRICAL CHARACTERISTICS (V = +3.0V to +3.6V, PECL loads = 50Ω +3.3V +25°C.) (Note PARAMETER SYMBOL Serial Data Rate SDI Parallel Output Data Rate ...
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SDH/SONET 1:16 Deserializer with Clock Recovery (V = +3.3V +25°C, unless otherwise noted RECOVERED DATA AND CLOCK PATTERN DATA CLOCK 1.64ns/div JITTER TOLERANCE vs. INPUT VOLTAGE 1 JITTER FREQUENCY = ...
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Deserializer with Clock Recovery PIN NAME 1, 15, 16, 17, 25, 33, 41, GND Ground 49, 57, 62 FIL+ Positive Filter Input. PLL loop filter connection. Connect a 1.0µF capacitor between FIL+ and FIL-. 3 FIL- Negative ...
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SDH/SONET 1:16 Deserializer with Clock Recovery V CC 50Ω SDI+ AMP SDI- 0 MUX SLBI AMP SLBI- I 50Ω SIS Figure 3. MAX3881 Functional Diagram Detailed Description The MAX3881 deserializer with clock recovery converts ...
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Deserializer with Clock Recovery although the jitter tolerance performance will be degraded. For interfacing with PECL signal levels, see Applications Information. The phase detector in the MAX3881 produces a volt- age proportional to the phase difference between the incoming ...
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SDH/SONET 1:16 Deserializer with Clock Recovery 50Ω termination (Figure 5). AC-coupling is also required to maintain the input common-mode level. Exposed-Pad Package The exposed-pad (EP), 64-pin TQFP incorporates fea- tures that provide a very low thermal-resistance path for ...
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SDH/SONET 1:16 Deserializer with Clock Recovery 0.01µF +3. OUT+ FIL MAX3866 IN+ PRE/POSTAMPLIFIER OUT- LOP TTL SYSTEM LOOPBACK EXTERNAL TERMINATION REQUIRED ONLY IF OVERHEAD CIRCUIT DOES NOT INCLUDE INTERNAL INPUT TERMINATION. THIS SYMBOL REPRESENTS A TRANSMISSION ...
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SDH/SONET 1:16 Deserializer with Clock Recovery 10 ______________________________________________________________________________________ Package Information ...
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... Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 11 © 2001 Maxim Integrated Products +3 ...