AT91SAM9261S-CU Atmel, AT91SAM9261S-CU Datasheet - Page 16

• Manufacturer Part Number: AT91SAM9261S-CU
• Description: ARM Microcontrollers - MCU BGA IND TEMP
• Manufacturer: Atmel
• Series: 91Sr

Specifications of AT91SAM9261S-CU

• Product Category: ARM Microcontrollers - MCU
• Rohs: yes
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 190 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 16 KB
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: BGA-217
• Mounting Style: SMD/SMT
• Interface Type: 2-Wire, I2S, SPI, USB
• Length: 15 mm
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 96
• Number Of Timers: 4
• Program Memory Type: ROM
• Factory Pack Quantity: 126
• Supply Voltage - Max: 1.32 V, 3.6 V
• Supply Voltage - Min: 1.08 V, 1.65 V, 2.7 V, 3 V

8.1
16
Embedded Memories
AT91SAM9261S
A first level of address decoding is performed by the Bus Matrix, i.e., the implementation of the
Advanced High performance Bus (AHB) for its Master and Slave interfaces with additional
features.
Decoding breaks up the 4 Gbytes of address space into 16 areas of 256 Mbytes. The areas 1 to
8 are directed to the EBI that associates these areas to the external chip selects NCS0 to NCS7.
The area 0 is reserved for the addressing of the internal memories, and a second level of decod-
ing provides 1 Mbyte of internal memory area. The area 15 is reserved for the peripherals and
provides access to the Advanced Peripheral Bus (APB).
Other areas are unused and performing an access within them provides an abort to the master
requesting such an access.
The Bus Matrix manages five Masters and five Slaves.
Each Master has its own bus and its own decoder, thus allowing a different memory mapping
per Master.
Regarding Master 0 and Master 1 (ARM926
assigned to the memory space decoded at address 0x0: one for internal boot, one for external
boot, one after remap. Refer to
Table 8-1.
Each Slave has its own arbiter, thus allowing a different arbitration per Slave.
Table 8-2.
Master 0
Master 1
Master 2
Master 3
Master 4
Slave 0
Slave 1
Slave 2
Slave 3
Slave 4
• 32 KB ROM
• 16 KB Fast SRAM
– Single Cycle Access at full bus speed
– Single Cycle Access at full bus speed
List of Bus Matrix Masters
List of Bus Matrix Slaves
Table 8-3
for details.
™
Instruction and Data), three different Slaves are
ARM926 Instruction
ARM926 Data
PDC
LCD Controller
USB Host
Internal SRAM
Internal ROM
LCD Controller and USB Host Port Interfaces
External Bus Interface
Internal Peripherals
6242ES–ATARM–11-Sep-09