PCA9555AHF,128 NXP Semiconductors, PCA9555AHF,128 Datasheet - Page 16

• Manufacturer Part Number: PCA9555AHF,128
• Description: Interface - I/O Expanders
• Manufacturer: NXP Semiconductors

Specifications of PCA9555AHF,128

• Rohs: yes
• Maximum Operating Frequency: 100 kHz
• Operating Supply Voltage: 1.65 V to 5.5 V
• Operating Temperature Range: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: HWQFN-24
• Operating Current: 160 mA
• Output Current: 25 mA
• Power Dissipation: 200 mW
• Product Type: I/O Expanders

NXP Semiconductors
Table 13.
T
[1]
[2]
PCA9555A
Product data sheet
Symbol
(dV/dt)
(dV/dt)
t
V
t
V
d(rst)
w(gl)VDD
amb
POR(trip)
DD(gl)
Level that V
Glitch width that will not cause a functional disruption when V
= 25
f
r

C (unless otherwise noted). Not tested; specified by design.
Recommended supply sequencing and ramp rates
Parameter
fall rate of change of voltage
rise rate of change of voltage
reset delay time
glitch supply voltage difference
supply voltage glitch pulse width
power-on reset trip voltage
DD
can glitch down to with a ramp rate of 0.4 s/V, but not cause a functional disruption when t
Glitches in the power supply can also affect the power-on reset performance of this
device. The glitch width (t
other. The bypass capacitance, source impedance, and device impedance are factors that
affect power-on reset performance.
how to measure these specifications.
V
is released and all the registers and the I
their default states. The value of V
0 V.
Fig 17. Glitch width and glitch height
Fig 18. Power-on reset voltage (V
POR
V
V
POR
POR
Figure 18
is critical to the power-on reset. V
(falling V
(rising V
V
DD
DD
DD
∆V
)
)
and
POR
V
DD(gl)
All information provided in this document is subject to legal disclaimers.
DD
Low-voltage 16-bit I
Table 13
Rev. 1 — 11 September 2012
Condition
Figure 15
Figure 15
Figure
V
Figure
V
Figure 17
Figure 17
falling V
rising V
DD
DD
w(gl)VDD
drops below 0.2 V or to V
drops to V
15; re-ramp time when
16; re-ramp time when
provide more details on this specification.
DD
DD
t
DD(gl)
w(gl)VDD
) and glitch height (V
POR
POR
POR(min)
= 0.5  V
Figure 17
)
POR
differs based on the V
2
C-bus I/O port with interrupt and weak pull-up
2
C-bus/SMBus state machine are initialized to
 50 mV
is the voltage level at which the reset condition
DD
.
and
SS
Table 13
[1]
[2]
DD(gl)
Min
0.1
0.1
1
1
-
-
0.7
-
provide more information on
) are dependent on each
DD
being lowered to or from
Typ
-
-
-
-
-
-
-
-
w(gl)VDD
PCA9555A
© NXP B.V. 2012. All rights reserved.
< 1 s.
Max
2000
2000
-
-
1
10
-
1.4
002aah331
time
002aah332
Unit
ms
ms
s
s
V
s
V
V
16 of 39
time
time